Simple PWM Question

You question may seem simple to you, but it isn't easily answered. It is not clear what you want to do nor do you tell which processor you use.

Different MSPs have different hardware modules, different triggers and internal wiring.

You seem to want to sample audio. There are several possible ways to do this, depending on the exact requirements.

There are several other threads about PWM and duty cycle. So if you want to use a timer PWM to trigger S&H and conversion, it again depends on the used CPU whether this is possible at all and how to do it. Maybe external wiring is required, maybe there are internal trigger sources available.

On some devices you can clock ADCLCK from a system clock source and therefore make the conversion cycle fit the requested sampling frequency, on others you'll need to output the timer PWM signal on a pin and route it to another pin for triggering the ADC.

About PWM creation, it basically goes this way:

- set up TxCCR0 to a value that fits your pwm frequency, Tx in UP mode.
- set up TxCCRx to a fraction of TxCCR0 value. This fraction defines the duty cycle. Output mode is either set/reset or reset/set.

The oputput is reset (or set, depending on outmode) when the timer hits TxCCR0 and is reset to 0, and will be set (or reset) when the timer reaches TxCCRx value. If TxCCR0 is 1000, a value of 500 for TxCCRx will give you 50% duty cycle. Note that you can either reach 100% duty cycle or 0% but not both, depending on the outmode. This is because at TxCCR0, the timer will be set back to 0 immediately, so set and reset will take place at the same time, one getting the preference.

Ich checked the datasheet.

There are two ways to drive the ADC12 with a given sample frequency.

The easiest one is to use A/M/SMCLK as clock source for ADC conversion clock. One sample takes 13 clock cycles plus the selected S&H time (SHT0/SHT1) See fig. 28-4 in the datasheet. With SMCLK = 1.048 MHz and 8 kHz sampling frequency, it makes 131 clock cycles per sample. You can select either 96 or 128 cycles S&H time, resulting in either 9.6kHz or 7.4kHz sample frequency. To get exactly 8kHz, you'd need to increase or decrease the clock.
In this mode, you have a free-running conversion and will get an interrupt each time a sampel is ready. But keep in mind that you only have 109 or 141 cpu cycles to handle the data. Even better is a setting with an ADCCLK divider o3 3 and a S&H time of 32, resulting in 135 clock cycles per conversion and 7.763kHz.

The other way is to use either timerA or TimerB. Here again two different approaches are possible.

One is to trigger conversion by an external source. This mode is selected by SHP=1. YOu can use Timer_A.OUT1, Timer_B.OUT0 or TImer_B.OUT1 to start s&h which then runs for the programmed number of cycles of the selected clock source (either ADC12OSC or A/M/SMCLK) and then starts a conversion. Next conversion is started with the next OUTx transition.
This way you can exactly control the distance of two samples (sampling frequency) but have limited control over the sampling time (and the resulting low pass characteristics). And you need a timer. When using TimerB, you can set it to twice the required frequency and set the outmod to toggle.

The most complex way is to use a timer PWM function. It is selected by SHP=0. Set up a timer (A or B) for the required sampling frequency (up mode). Then set up the CCR1 to the required duty cycle and run it in reset/set outmode. The percentage of the value of CCR1 compared to CCR0 is the duty cycle.
TxR starts with 0 and counts up. When it reaches CCR1 value, OUT1 is reset. When it reaches CCR0 value, OUT1 is set, sampling starts, TxR is reset to 0 and starts counting up again. When it again reaches CCR1, OUT1 is reset, sampling stops (hold phase) and conversion starts, being finished 13 ADC12clk cycles later (and eventually causing an interrupt). When TxR reaches CCR0, OUT1 is set again, sampling starts again etc.
This way you can exactly define sampling frequency and also the sample time (which forms a low pass filter for the incoming signal). Just keep CCR1 low enough so in the remaining time (CCR1 to CCR0) the conversion can be completed.

It is possible to get a good result with the first approach when using ADC12OSC as clock source. It is in the range of 3.7..6.3MHz, so it requires some manual calibration, but its higher frequency than your main clock might allow proper 8kHz in a given combination of SHT and ADC12DIV.
I didn't find any information about calibration values for ADC12OSC, neither in a TLV structure nor in INFO memory, so you might need to write an auto-calibration function that measures the time betweeen two free-running calculations for an exact measurement of ADC12OSC before you use it.