MSP430F67751IPZR External crystal not working

Muthu,

then maybe your configuration of the clock is wrong. The crystal itself isn't the problem in most cases.
Post your initialization of the clock module. Please use the syntax highlighter in richt text formatting when inserting code.

Dennis

Btw.: The crystal's frequency is 32.768 kHz, not 32.678 kHz, but this might be just a typo.

Hi Dennis,

Thank you for reply, I will share Code once I get conformation our software team.

Muthu,

Did you have a look at the code example for using the external crystal? It is

• MSP430F677x_UCS_6.c

//******************************************************************************
//  MSP430F67791 Demo - UCS, XT1 sources ACLK. Toggles P5.3
//
//  Description: This program demonstrates using XT1 to source ACLK
//  ACLK = LFXT1 = 32,768Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *//
//
//                MSP430F67791
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz
//          --|RST          XOUT|-
//            |                 |
//            |             P1.2|--> ACLK = ~32kHz
//            |                 |
//            |             P5.3|-->LED
//
//   C. Fu
//   Texas Instruments Inc.
//   October 2012
//   Built with CCS Version: 5.1.0 and IAR Embedded Workbench Version: 5.51
//******************************************************************************
#include <msp430.h>

void main(void)
{
    WDTCTL = WDT_ADLY_1000;                 // WDT 1000ms, ACLK, interval timer
    SFRIE1 |= WDTIE;                        // Enable WDT interrupt

    // Setup P5.3 output, P1.2 ACLK
    P5DIR |= BIT3;                          // Set P5.3 to output direction
    P5OUT &= ~BIT3;                         // Clear P5.3
    P1DIR |= BIT2;                          // ACLK set out to pin
    P1SEL0 |= BIT2;                          // P1.2 for debugging purposes.

    // Setup LFXT1
    UCSCTL6 &= ~(XT1OFF);                   // XT1 On
    UCSCTL6 |= XCAP_3;                      // Internal load cap

    // Loop until XT1, XT2 & DCO stabilizes
//    do
//    {
//        UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
//        // Clear XT2,XT1,DCO fault flags
//        SFRIFG1 &= ~OFIFG;                  // Clear fault flags
//    } while (SFRIFG1 & OFIFG);              // Test oscillator fault flag
    UCSCTL6 &= ~(XT1DRIVE_3);               // XT1 stable, reduce drive strength

    __bis_SR_register(LPM3_bits | GIE);     // Enter LPM3 w/ interrupts
    __no_operation();                       // For debugger
}

// Watchdog Timer interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = WDT_VECTOR
__interrupt void watchdog_timer(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(WDT_VECTOR))) watchdog_timer (void)
#else
#error Compiler not supported!
#endif
{
    P5OUT ^= BIT3;                          // Toggle P5.3 using exclusive-OR
}

This code is tested since it is from TI itself. The code examples can be found here:

Dennis

Dennis, be careful with what you advise. This example is not usable for a proper clock setup. Also there are variables as load-capacitance which are unknown by the example.
Hardware failures as crystal mounting, additional capacitors etc., are the first to suspect.

Yes, of course there can be hardware related problems, too. Just from experience it is a wrong or missing initialization in most cases.
What do you mean with the "not usable example"? To be honest: I just copied it from the code examples, but what is wrong with that? Only for testing if the crystal is actually running.

Dennis

The example has commented out the oscillator test, nice to view the oscillator startup but not usable in a real program.
The OP doesn’t talk about further oscillator setup, FLL & DCO, if then you get another scenario.
The load-capacitance selected is probably not the correct one.

Yes, OK - I agree with you that this is no copy paste code for the application he is actually running and it wasn't intended to be that. But it could help to see if the crystal is running at all. Not more.

Dennis

Hi Dennis and Leo bosch,
Thank for the information.

I want configure 16MhZ clock frequency from 32.768KhZ external crystal frequency. Is that any recommendation and setting to handle with care while converting 32.768KHz to 16MHz clock frequency.

Already we tried sample codes that is what I am exploring right configure and crystal, if can else.

You can first setup the FLL using the REFO as reference instead of the Crystal.
When this works change to the crystal.
And to be precise you will get a DCO frequency of 15.990.784Hz.

Leo Bosch,

When use REFO Clock to configure FLL is working fine,If switched to XT1 clock Flag error Bit was set.

Did you change your clock setup? What you show here is wrong, and also I think your Load cap must be ‘2’.

Yes I changed clock setup, Here I have pasted flag of register value,

UCSCTL7 0x0701 UCS Control Register 7 [Memory Mapped]
XT2OFFG 0 High Frequency Oscillator 2 Fault Flag
XT1LFOFFG 0 XT1 Low Frequency Oscillator Fault Flag
DCOFFG 1 DCO Fault Flag

DCOFFG set means you have selected an FLL configuration and RSEL setting that doesn't allow the DCO running with the required speed. It did hit the upper or lower limit of the DCOx bits. Or the DCO hasn't yet moved up from its initial setting.
XT1LFOFFG being clear means the crystal seems to run (or is switched off, in which case the FLL would run from REFO)

Looking at your clock init code is required to further interpret the situation.