MSP432P401R - need some help with setting interrupts in the NVIC register

Hi everyone!

I'm working with the MSP432 LaunchPad now and I want to use the ADC14.

I must admit, that migrating to the new 432 family isn't that easy for me as I am only used to the 430 so far. Never used something like the startup-file.

I plan to use the interrupt from the ADC14 module.

What I did so far: From the code examples I could get an idea of what I have to change, so I opened the header file for the P401R and searched for

INT_ADC14

this is 40. Now I opened the startup file and added

/* External declarations for the interrupt handlers used by the application. */
extern void ADC14_ISR_Handler( void );
/* To be added by user */

I also added

...
defaultISR,                                /* EUSCIA3 ISR               */
defaultISR,                                /* EUSCIB0 ISR               */
defaultISR,                                /* EUSCIB1 ISR               */
defaultISR,                                /* EUSCIB2 ISR               */
defaultISR,                                /* EUSCIB3 ISR               */
ADC14_ISR_Handler,                         /* ADC14 ISR                 */
defaultISR,                                /* T32_INT1 ISR              */
defaultISR,                                /* T32_INT2 ISR              */
defaultISR,                                /* T32_INTC ISR              */
defaultISR,                                /* AES ISR                   */
...

and this is located at entry 40 in this list now (starting from 0). Another question here: Why is there

defaultISR                                 /* Reserved 64               */

listed in the table? I would understand 63, but why 64? The user's guide says, the NVIC controller can handle up to 64 interrupts, so 0 to 63.

Or is it because 0 means no pending interrupt and therefore it is 1 to 64?

In the main.c I added

void ADC14_ISR_Handler( void )
{
  // Future ADC14 ISR code
}

And now I do not understand this line

NVIC_ISER0 = 1 << ((INT_ADC14 - 16) & 31);         // Enable ADC interrupt in NVIC module

I understand that there are two 32 bit registers for NVIC, giving 64 bits in total. We will now use the lower NVIC register, so 0 to 31. The operation performed there is the following

NVIC_ISER0 = 1 << ((INT_ADC14 - 16) & 31);         // Enable ADC interrupt in NVIC module

NVIC_ISER0 = 1 << ((40 - 16) & 31);
NVIC_ISER0 = 1 << (24 & 31);
NVIC_ISER0 = 1 << (0001 1000 & 0001 1111); // 24 & 31
NVIC_ISER0 = 1 << 0001 1000; // 24
NVIC_ISER0 = 1 << 24;
NVIC_ISER0 = 0000 0001 0000 0000 0000 0000 0000 0000;

The "& 31" is to ensure that the number is not greater than the maximum of 31 bits in the lower NVIC register. I looked at another code example for a timer module and there it was

NVIC_ISER0 = 1 << ((INT_TA0_N - 16) & 31);

So almost identical with exception of INT_TA0_N which is 25 - this would lead to a bit shift of 9, setting the 10th bit in NVIC_ISER0. So why is always 16 subtracted?

And what would happen if I had

INT_DMA_INT0

for example? This is 50 and would lead to

NVIC_ISER0 = 1 << ((INT_DMA_INT0 - 16) & 31);

NVIC_ISER0 = 1 << ((50 - 16) & 31);
NVIC_ISER0 = 1 << (34 & 31);
NVIC_ISER0 = 1 << (0010 0010 & 0001 1111); // 34 & 31
NVIC_ISER0 = 1 << 0000 0010; // 2
NVIC_ISER0 = 1 << 2;
NVIC_ISER0 = 0000 0000 0000 0000 0000 0000 0000 0100;

Can someone explain?

Thanks in advance!

Dennis