MSP430F5529 and 24Mhz crystal oscillator in bypass mode

Hi Community,

I am stuck with a problem on my custom mspf5529 board.

My board has a 24MHz clock source connected to P5.2 (XT2IN).  Everything is working so far, but when I select to source MCLK from XT2 my mcu goes into failsafe mode. Strange thing is, when I divide the clock by 2 everything is working (checked with a scope). Power is set to PMM_CORE_LEVEL_3 before.

Any ideas?

Thanks in advance!

Chris

	__bis_SR_register(SCG0 | SCG1);             /// Disable the FLL control loop

	P5SEL |= BIT2 | BIT3;   //  set for XT2, P5 bits 2 & 3
	P5SEL |= BIT4 | BIT5;	//	set for XT1, P4 bits 3 & 5
	P5OUT &= ~BIT2 & ~BIT3;

	UCSCTL1 |= DISMOD;					        // Disable Modulation
	/* Set XT2BYPASS (clock source on XT2), XT1DRIVE_3 and 2pF load capacitor */
	UCSCTL6 = XT2BYPASS + XT1DRIVE_3 + XCAP_0;

//	/* Initialize DCO to 24.00MHz */
//  UCSCTL3 = SELREF__REFOCLK;    // select REFO as FLL source
//	UCSCTL0 = 0x0000u;                        // Set lowest possible DCOx, MODx
//	UCSCTL1 = DCORSEL_5;                      // Set RSELx for DCO = 50 MHz
//	UCSCTL2 = 732u;                           // Set DCO Multiplier for 24MHz
//										      // (N + 1) * FLLRef = Fdco
//											  // (732 + 1) * 32768 = 24.00MHz
//	__bic_SR_register(SCG0);                  // Enable the FLL control loop

/* Worst-case settling time for the DCO when the DCO range bits have been
*  changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
*  UG for optimization.
* 32*32*25MHz/32768Hz = 781250 = MCLK cycles for DCO to settle
* */
// __delay_cycles(781250u);

	/* Loop until XT1,XT2 & DCO fault flag is cleared */
	do {
		if (UCSCTL7 & XT2OFFG)
			_no_operation();
		if (UCSCTL7 & XT1LFOFFG)
			_no_operation();
		if (UCSCTL7 & XT1HFOFFG)
			_no_operation();
		if (UCSCTL7 & DCOFFG)
			_no_operation();

		UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
		// Clear XT2,XT1,DCO fault flags
		SFRIFG1 &= ~OFIFG;                      // Clear fault flags
	} while (SFRIFG1 & OFIFG);                    // Test oscillator fault flag

UCSCTL4 |= SELA__XT1CLK | SELS__XT2CLK | SELM__XT2CLK;