MSP430 SPI slave MODE0 issue - bit shifting

I have configured MSP430F5529 Experimenter Board as SPI slave in MODE0 configuration.

So my program is , whenever I receive a byte from master a constant value 0xAA is put into TX buffer of slave which will be shifted out in the next transaction. I can see that the SPI master always get 0x55 (which is 1 bit shifted of 0xAA). I probed the SPI lines to get an idea on what's going on.

So here , in SPI MODE0 , data sampling -> rising edge, data toggling -> falling edge. 

the slave is receiving the data from master properly, but transmission of 0xAA from slave is shown MISO (blue waveform).

Explanation:

*. Since the toggling edge is falling , slave skips the first rising edge and the data from slave is made available only on the first falling edge,

*. By that time master sampled the first bit in the first clock itself which is read as 0.

*. This is why I'm missing the first bit, or the Byte gets shifted by 1 bit.

Does MSP430 has some kind of limitation in MODE0 ?

Hers's my code

int main(void)
{
    WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer
    Clock_Init();

    P4SEL |= BIT0 + BIT4 + BIT5;                            // P4.5,4,,0 option select

    UCA1CTL1 |= UCSWRST;                      // **Put state machine in reset**
    UCA1CTL0 |= UCSYNC+UCMSB+UCCKPH;
    UCA1CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
    UCA1IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt

    __enable_interrupt();        // enable interrupts
    while(1);
}

#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)

{
    switch(__even_in_range(UCA1IV,4))
    {
    case 0:break;                             // Vector 0 - no interrupt
    case 2:                                   // Vector 2 - RXIFG
        raw_buff = UCA1RXBUF;
        while (!(UCA1IFG&UCTXIFG));
        UCA1TXBUF = 0xaa;
        break;
    case 4:break;                             // Vector 4 - TXIFG
    default: break;
    }
}