i used circuit above to test SD24 precision,but when tie A0.0+ to A0.0- ,there is a drift about 24/65536*1.16 = 0.4mv in my result, why this happens?
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i used circuit above to test SD24 precision,but when tie A0.0+ to A0.0- ,there is a drift about 24/65536*1.16 = 0.4mv in my result, why this happens?
Kissn Liu,
There certainly should not be this much of an offset/drift on the SD24 of the MSP430i2041, especially if the low_level_init function is properly being included in your project (for calibration purposes).
I modified one of the simple code examples (attached below) to save the values in a buffer in RAM. Additionally, I was testing using the MSP-TS430PW28B target board with the MSP-FET emulator connected for debugging. Using this code, I was not seeing any value outside the range of 0xFFF4 to 0xFFF6. I have also attached my output data file from the RAM buffer I mentioned previously.
Can you provide similar data for me to see your drift?
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//******************************************************************************
// MSP430i20xx Demo - SD24, Single Conversion on a Single Channel, Use ISR
//
// Description: This program uses the SD24 module to perform a single
// conversion on a single channel. A SD24 interrupt occurs when a conversion
// has completed.
//
// Test by applying a voltage to the input channel and setting a breakpoint
// at the indicated line. Run program until it reaches the breakpoint, then use
// the debugger's watch window to view the conversion results.
//
// Results (upper 16 bits only) are stored in the variable "results"
//
// ACLK = 32kHz, MCLK = SMCLK = Calibrated DCO = 16.384MHz, SD_CLK = 1.024MHz
// * Ensure low_level_init.c is included when building/running this example *
//
// Notes: For minimum Vcc required for SD24 module - see datasheet
// 100nF cap btw Vref and AVss is recommended when using 1.2V ref
//
// MSP430i20xx
// -----------------
// /|\| |
// | | |
// --|RST |
// | |
// Vin1+ -->|A0.0+ VREF |---+
// Vin1- -->|A0.0- | |
// | | -+- 100nF
// | | -+-
// | | |
// | AVss |---+
//
// T. Witt
// Texas Instruments, Inc
// September 2013
// Built with Code Composer Studio v5.5
//******************************************************************************
#include "msp430.h"
#define BUFFER_SIZE 256
unsigned int results[BUFFER_SIZE]; // SD24 Conversion Result Buffer
unsigned int index = 0; // Buffer index
void main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
SD24CTL = SD24REFS; // Internal ref
SD24CCTL0 |= SD24SNGL | SD24DF | SD24IE; // Enable interrupt
__delay_cycles(3200); // Delay ~200us for 1.2V ref to settle
while(1) {
SD24CCTL0 |= SD24SC; // Set bit to start conversion
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
__no_operation(); // For debugger
if(index > (BUFFER_SIZE - 1)) { // If index has reached end of buffer
index = 0; // Reset index
__no_operation(); // SET BREAKPOINT HERE
}
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=SD24_VECTOR
__interrupt void SD24_ISR(void) {
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SD24_VECTOR))) SD24_ISR (void)
#else
#error Compiler not supported!
#endif
switch (__even_in_range(SD24IV,SD24IV_SD24MEM3)) {
case SD24IV_NONE: break;
case SD24IV_SD24OVIFG: break;
case SD24IV_SD24MEM0:
results[index++] = SD24MEM0; // Save CH0 results (clears IFG)
break;
case SD24IV_SD24MEM1: break;
case SD24IV_SD24MEM2: break;
case SD24IV_SD24MEM3: break;
default: break;
}
__bic_SR_register_on_exit(LPM0_bits); // Wake up from LPM0
}
Kissn Liu,
Attached below is the schematic for the target board. I have connected pins 1 & 2 (A0.0+ and A0.0-) to the GND pins of J5.
This emulates exactly what you are showing on your schematic.
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