Hi guys,
I have a question about using the MSP430F67791A. I am also using an external crystal. I want to use the SD24B ADC with a really high sampling rate but works for a really short time to get measurements. But I also want the ADC triggered by the RTC calendar mode with every 1 min interval(if could be changed to any intervals will be great). The ADC works fine without the RTC. I am trying to trigger the ADC by changing a status parameter to start conversion, but the ADC is not triggered. I am new to the RTC, any help will be great. Thanks. Below is my code
#include <msp430.h>
#include <stdio.h>
#include <math.h>
#include <string.h>
unsigned int status = 0; // The status conditions
unsigned int index = 0;
unsigned int CurrentCount[datapoints]; // How many datapoints converted by the ADC, just for test
unsigned int CurrentIndex[datapoints]; // How many indexes of datapoints, just for test
unsigned int Ch0results[datapoints]; // The channel0 of data output from the ADC
unsigned int Ch1results[datapoints]; // The channel1 of data output from the ADC
unsigned int Ch2results[datapoints]; // The channel2 of data output from the ADC
void main(void)
{
WDTCTL = WDTPW | WDTHOLD;
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop*
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 = FLLD_1 | 255; // Set DCO Multiplier for 8.388608MHz
// (N + 1) * FLLRef = Fdco
// (255 + 1) * 32768 = 8.388608MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
__delay_cycles(262144);
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
SD24BCTL0 = SD24REFS | SD24SSEL_1; // Select internal REF
// Select SMCLK as SD24_B clock source
SD24BCCTL0 = SD24SNGL | SD24SCS_5; // Single conversion, group 1
SD24BCCTL1 = SD24SNGL | SD24SCS_5; // Single conversion, group 1
SD24BCCTL2 = SD24SNGL | SD24SCS_5; // Single conversion, group 1
SD24BIE |= SD24IE2;
__delay_cycles(0x3600);
TA0CTL = TASSEL_2 | TAIE;
TA0CCTL0 = CCIE;
TA0CCR0 = 0x919;
RTCCTL1 &= ~RTCHOLD;
TA0CTL |= MC_1 | TACLR;
RTCCTL0_H = RTCKEY_H;
RTCCTL0_L = RTCTEVIE | RTCRDYIE | RTCAIE;
RTCCTL1 |= RTCMODE | RTCTEV_0 | RTCHOLD | RTCSSEL0; // 32-kHz clock reference
RTCYEAR = 2015;
RTCMON = 05;
RTCDAY = 26;
RTCDOW = 02;
RTCHOUR = 12;
RTCMIN = 00;
RTCSEC = 45;
RTCCTL1 &= ~(RTCHOLD);
RTCCTL0_H = 0;
__bis_SR_register(LPM3_bits | GIE);
if (status == 1) // Status condition changes to allow the ADC start conversion
{
while (index <= 60)
{
SD24BCTL1 |= SD24GRP1SC; // Set bit to start conversion for single conversion mode
}
TA0CTL &= ~MC_1; // Disable the Timer
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) TIMER0_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch (__even_in_range(TA0IV, 14))
{
case TA0IV_NONE: break; // No interrupt
case TA0IV_TA0CCR1: break; // TA0CCR1_CCIFG
case 4: break; // Reserved
case 6: break; // Reserved
case 8: break; // Reserved
case 10: break; // Reserved
case 12: break; // Reserved
case TA0IV_TA0IFG: // TA0IFG
CurrentCount[index] = (TA0R - 0x1);
CurrentIndex[index] = index;
++index;
break;
default: break;
}
__bic_SR_register_on_exit(LPM3_bits); // Exit LPM3
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=SD24B_VECTOR
__interrupt void SD24BISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SD24B_VECTOR))) SD24BISR (void)
#else
#error Compiler not supported!
#endif
{
switch (SD24BIV)
{
case SD24BIV_SD24OVIFG: // SD24MEM Overflow
break;
case SD24BIV_SD24TRGIFG: // SD24 Trigger IFG
break;
case SD24BIV_SD24IFG0: // SD24MEM0 IFG
break;
case SD24BIV_SD24IFG1: // SD24MEM1 IFG
break;
case SD24BIV_SD24IFG2: // SD24MEM2 IFG
Ch0results[index-1] = SD24BMEMH0;
Ch0results[index-1] = (Ch0results[index-1] << 8) | ((SD24BMEML2 >> 8) & 0x00FF);
Ch1results[index-1] = SD24BMEMH1;
Ch1results[index-1] = (Ch1results[index-1] << 8) | ((SD24BMEML2 >> 8) & 0x00FF);
Ch2results[index-1] = SD24BMEMH2;
Ch2results[index-1] = (Ch2results[index-1] << 8) | ((SD24BMEML2 >> 8) & 0x00FF);
break;
}
SD24BCTL1 &= ~SD24GRP1SC; // Clear bit for next conversion
__bic_SR_register_on_exit(LPM3_bits); // Exit LPM3
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=RTC_VECTOR
__interrupt void rtc_isr(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(RTC_VECTOR))) rtc_isr (void)
#else
#error Compiler not supported!
#endif
{
switch (__even_in_range(RTCIV, 16))
{
case RTCIV_NONE: // No interrupts
break;
case RTCIV_RTCOFIFG: // RTCOFIFG
break;
case RTCIV_RTCRDYIFG: // RTCRDYIFG
__no_operation();
break;
case RTCIV_RTCTEVIFG: // RTCEVIFG
status = 1;
__no_operation();
break;
case RTCIV_RTCAIFG: // RTCAIFG
__no_operation();
break;
case RTCIV_RT0PSIFG: // RT0PSIFG
break;
case RTCIV_RT1PSIFG: // RT1PSIFG
break;
case 16: break; // Reserved
default: break;
}
__bic_SR_register_on_exit(LPM3_bits); // Exit LPM3
}
