poor duty cycle of clock

Viney,

even if the FLL does not have the frequency you expected, the UCB1 will normally not only output 2 or 3 clocks instead of 8. Could you show your complete code please? I would guess the problem is located somewhere else. (Please use the code-insertion tool in rich text formatting for inserting code)

Dennis

Dennis, Thanks for helping out.   


 CLK_Speed = 24000000;

    USBHAL_initClocks(CLK_Speed);
 
void USBHAL_initClocks(uint32_t mclkFreq)
{
	UCS_initClockSignal(
	   UCS_FLLREF,
	   UCS_REFOCLK_SELECT,
	   UCS_CLOCK_DIVIDER_1);

	UCS_initClockSignal(
	   UCS_ACLK,
	   UCS_REFOCLK_SELECT,
	   UCS_CLOCK_DIVIDER_1);

    UCS_initFLLSettle(
        mclkFreq/1000,
        mclkFreq/32768);

}

I used the above code which was written for 8MHz and changed 8MHz to 24MHz. Sorry the MCLK and SMCLK get stabilized at 24MHz.

Regards

Viney Chaddha

Viney,

did you adjust your core voltage for 24MHz? You will need to set it to PMMCOREV_3.

Dennis

Dennis,
No that has not been done. Will do that and try. Thanks once again. In case after that also if i face a problem I will get back to you.
Regards
Viney Chaddha

Dennis,
Set the level to 3 but didn't sort out the problem fully. there was an improvement but again some cycles were seen as missed and the duty cycle wasn't stable.
Regards
Viney Chaddha

What signal do you see when you route SMCLK directly to P2.2?

(Somewhat unequal duty cycles are to be expected with the FLL, because the modulator switches between two frequencies.)

Clemens,

I see a 8 MHz clock irrespective of the number that I feed in the earlier loop. The Clock is mostly clean but with some pulses missing some times. Screen shot attached.

Your logic analyzer's sample rate of 16 MHz will never show any signal above 8 MHz.

To measure a 24 MHz signal, you need a sample rate of more than 48 MHz.

Clemens,
but if I run the logic analyzer at 24 MHz then at least i should be able to see the 12 MHz. I see the glitched in the 8 MHz clock only as seen in the picture. Also If i source the SMCLK by XT2 Crystal I see a much cleaner clock as compared to the FLL 4 MHz (Both running at 4 MHz, for example).

Why do I see missed clock at 8 MHz as seen in the picture above.
Regards
Viney Chaddha

Did you read what I wrote about the FLL above?

8 MHz is too near the Nyquist frequency.