Timer_D Issue

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 *
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
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 * for an API functional library-approach to peripheral configuration.
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//******************************************************************************

#include <msp430.h> 



//#define BASIC_MODE
#define MULT_16

#define USE_DCO_16MHz
//#define USE_DCO_8MHz
//#define USE_DCO_1MHz

void F5172_config_VCore(void);
void SetVcoreUp(unsigned int level);
void F5172_config_CLK(void);

/*
 * main.c
 */
void main(void) {
    WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer
    F5172_config_VCore();			// Setup VCore to correct range for desired frequency

    F5172_config_CLK();
    P2SEL |= BIT0 + BIT3;
    P2DIR |= BIT0 + BIT3;

    TD0CTL0 = TDSSEL_2			// Use SMCLK
    		+ CNTL_0			// 16-bit timer
			+ ID_0				// Divide by 1
			+ MC_0;				// Halt timer

#ifdef BASIC_MODE
    TD0CTL1 |= TDCLKM_0;		// TD clock is internal hi-res clock
#else
    TD0CTL1 |= TDCLKM_1;		// TD clock is internal hi-res clock
    TD0HCTL1 |= TDHCLKCR;		// Needed for regulated mode with CLK > 15 M
#endif

#ifndef BASIC_MODE
    TD0HCTL0 = TDHFW   			// Fast wake up mode
    		+ TDHD_0 			// Divider to 1
			+ TDHM_0			// Multiply by 16
			+ TDHREGEN			// Regulated mode
			+ TDHEAEN
			+ TDHEN;			// Enable Hi-Res

#ifdef MULT_16
    TD0HCTL0 |= TDHM_1;
    TD1HCTL0 = TDHM_1;			// Multiply by 16. Part of the workaround
#endif


    TD1HCTL1 |= TDHCLKCR;		// Needed for regulated mode with CLK > 15 M

#endif

    TD1CTL1 = TDCLKM_2;			// TD1 clock - AUX clock from master
    TEC1XCTL2 |= TECAXCLREN;	// Enable synchronized clear

    TD0CTL1 |= TD2CMB;
    TD0CCR0 = 200;
    TD0CCR1 = 40;
    TD0CCR2 = 80;
    TD0CCTL2 |= OUTMOD_7;		// Reset/Set

    TD1CTL1 |= TD2CMB;
    TD1CCR0 = 200;
    TD1CCR1 = 40;
    TD1CCR2 = 80;
    TD1CCTL2 |= OUTMOD_7;








#ifndef BASIC_MODE
    int i = 0;
    TD0CTL0 |= MC_1;		// Reset/Set
    for (i=0;i<12;i++);		// Delay workaround
    TD0CTL0 |= TDCLR;		// Clear Timer to sync
#else
    TD0CTL0 |= MC_1 + TDCLR;		// Reset/Set
#endif


       while(1){




       }

}

void F5172_config_VCore(void)
{
  //
  // Change core voltage one level at a time.
  //
  SetVcoreUp (0x01);
  SetVcoreUp (0x02);
  SetVcoreUp (0x03);
}


void SetVcoreUp(unsigned int level)
 {
   //
	//	Configure VCORE register for desired core voltage level
	//
   PMMCTL0_H = PMMPW_H;												 // Open PMM registers for write
   SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;     // Set SVS/SVM high side new level
   SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;						 // Set SVM low side to new level
    while ((PMMIFG & SVSMLDLYIFG) == 0);								 // Wait till SVM is settled
   PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);								     // Clear already set flags
   PMMCTL0_L = PMMCOREV0 * level;								  		 // Set VCore to new level
   if ((PMMIFG & SVMLIFG))											 	 // Wait till new level reached
     while ((PMMIFG & SVMLVLRIFG) == 0);
   SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;	 // Set SVS/SVM low side to new level
   PMMCTL0_H = 0x00;													 // Lock PMM registers for write access
 }



void F5172_config_CLK(void)
{

  //
  // Configure basic CLK registers. ACLK and DCO source = REF0. Select DCO range for required system frequency
  //
  UCSCTL3 = SELREF_2;                       // Set DCO FLL reference = REFO
  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO
  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_7;                      // Select DCO range 25MHz operation

  //
  // Configure registers for 16MHz operation
  //
  #ifdef USE_DCO_16MHz
  UCSCTL2 = FLLD_1 + 487;                   // Set DCO Multiplier for 16MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (487 + 1) * 32768 = ~16MHz
                                            // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  //
  //  Worst-case settling time for the DCO when the DCO range bits have been  changed is n x 32 x 32 x f_MCLK / f_FLL_reference.
  //  See UCS chapter in 5xx UG for optimization.
  //
  __delay_cycles(500000);					// 32 x 32 x 16 MHz / 32,768 Hz ~ 500000 MCLK cycles for DCO to settle
  #endif // USE_DCO_16MHz


  #ifdef USE_DCO_8MHz

  UCSCTL2 = FLLD_1 + 243;                   // Set DCO Multiplier for 16MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (243 + 1) * 32768 = ~8MHz
                                            // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 8 MHz / 32,768 Hz ~ 250000 MCLK cycles for DCO to settle
  __delay_cycles(250000);
  #endif // USE_DCO_8MHz

  #ifdef USE_DCO_1MHz
    UCSCTL2 = FLLD_1 + 30;                   // Set DCO Multiplier for 16MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (30 + 1) * 32768 = ~1MHz
                                            // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 1 MHz / 32,768 Hz ~ 31250 MCLK cycles for DCO to settle
  __delay_cycles(31250);
  #endif // USE_DCO_1MHz

  #ifdef USE_VLO
  UCSCTL4 |= SELA_1 		// ACLK = VLO
  UCSCTL5 |= DIVA_1 		// ACLK/2
  #endif //USE_VLO

  //
  // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
  //
  do
  {
    UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
}


// Timer0_D1 Interrupt Vector (TDIV) handler
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMER0_D1_VECTOR
__interrupt void TIMER0_D1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER0_D1_VECTOR))) TIMER0_D1_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(TD0IV,30))
  {
    case  0: break;                          // No interrupt
    case  2: break;                          // CCR1 not used
    case  4: break;                          // CCR2 not used
    case  6: break;                          // reserved
    case  8: break;                          // reserved
    case 10: break;                          // reserved
    case 12: break;                          // reserved
    case 14: break;
    case 16: break;
    case 18:                                 // Clock fail low
      while(1);                              // Input ref clock freq too low; trap here
    case 20:                                 // Clock fail high
      while(1);                              // Input ref clock freq too high; trap here
    case 22:                                 // Hi-res freq locked
      // Hi-Res freq locked; now configure ports to output PWMs at TD0/TD1
      P1SEL |= BIT6 + BIT7;                  // P1.6/TD0.0, P1.7,TD0.1, options select
      P1DIR |= BIT6 + BIT7;                  // Output direction
      P2SEL |= BIT0 + BIT1 + BIT2 + BIT3;    // P2.0/TD0.2, P2.1/TD1.0, P2.2/TD1.1, P2.3/TD1.2, options select
      P2DIR |= BIT0 + BIT1 + BIT2 + BIT3;    // Output direction

      __bic_SR_register_on_exit(LPM0_bits + GIE);  // Exit LPM0 on return to main

      break;
    case 24: break;                          // Hi-res freq unlocked
    case 26: break;                          // reserved
    case 28: break;                          // reserved
    case 30: break;                          // reserved
    default: break;
  }
}