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MSP432 SPI max frequency

da
Expert 2780 points

Hi

Frequency of MSP432 of SPI slave and master of the bit clock (fUCxCLK) how about you some?

I can not be calculated from the notes of the data sheet.
fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).

regards.

  • 0
    Guru 74080 points

    Look at the first page of the datasheet - it is 16Mbps:

    Dennis

  • 0
    Guru 46710 points
    If you assume that both master and slave chips are msp432 then tVALID=1ns and tSU=25ns meaning tLO/HI=26ns (at VCORE 1.4V). So indeed you _can_ calculate fUCxCLK
  • 0 in reply to Ilmars
    Expert 2780 points

    thanks.

    When tLO / HI is to 26ns, fUCxCLK will be 19.6MHz.
    Will come out is "up to 16Mbps" the difference between the data sheet, but so Will you sure?

    26ns x 2 = 51ns
    1 / 51ns = 19.608...MHz

  • 0 in reply to da
    Guru 46710 points
    >sure?

    To be honest - no. I just quickly demonstrated that you _can_ calculate and datasheet have all the data for that. Maybe I missed to account for slave hold time or something like that. Note that there are two eUSCI timing data tables: master (Table 5-48) and slave (Table 5-49) . You are advised to re-check data and recalculate.

    16MHz specified is very fast especially taking in account that particular chip is low power.

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