Other Parts Discussed in Thread: MSP430FR5969
Hi,
I want to read 2 voltage input with the ADC every 1ms. My code seems work but when I try to read the input every 10 ms there is some problems.
The first 20 samples are ok afrer that the Timer seems stop to work for about 80 ms and after that it restart to work for another 20 sample. So I have 20 samples every 100ms and I don't understand why . I'm using the launchpad( MSP430FR5969) with an external 16 mH crystal and this is my code :
#include <msp430.h>
volatile int ADC_A2[100]={0};
volatile int ADC_A12[100]={0};
volatile unsigned int i=0;
int main(void)
{
//SET PORT
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode to activate previously configured port settings
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
//Port 1
P1DIR |= BIT0;
//Port 3
//P3DIR = 0b00000000;
P3SEL1 |= BIT0;
P3SEL0 |= BIT0;
P2SEL1 |= BIT2;
P2SEL0 |= BIT2;
//Port J
PJSEL0 |= BIT6 | BIT7; // External Cristall XT2
FRCTL0 = FWPW+NACCESS_1; //SET FRAM to WORK WITH HIGH CLOCK
//SET CLOCK SURCE
CSCTL0_H = CSKEY >> 8; // Unlock CS registers
CSCTL1 = DCOFSEL_6; // Set DCO to 8MHz (not used)
CSCTL2 = SELA__VLOCLK|SELS__HFXTCLK | SELM__HFXTCLK; // SMCLK = HFXT and MCLK = HFXT
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1
CSCTL4 = HFXTDRIVE_3 | HFFREQ_2; // Maximum drive strength HFXT oscillator
CSCTL4 &= ~(HFXTOFF); // Disable Crystall bypass
CSCTL4 |= LFXTOFF ;
do
{
CSCTL5 &= ~(LFXTOFFG |HFXTOFFG); // Clear XT1 and XT2 fault flag
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1&OFIFG); // Test oscillator fault flag until the ext. clock is ready
CSCTL0_H = 0; // Lock CS registers
//SET CLOCK
TA0CCTL0 = CCIE; // TACCR0 interrupt enabled
TA0CCR0 = 50000; // Value to compare with the timer to generate interrupt
TA0CTL = TASSEL__SMCLK |ID__8| MC__UP; // select SMCLK, Divide SMCLK/8, UP mode
TA0EX0 = TAIDEX_1; // DIV2 : So timer_CLK = SMCLK/16
//ADC
//Set reference
while(REFCTL0 & REFGENBUSY); // If ref generator busy, WAIT
REFCTL0 |= REFVSEL_1 | REFON; // Select internal ref = 2.0V and Internal Reference ON
// Configure ADC12
ADC12CTL0 = ADC12SHT1_2|ADC12SHT0_2 |ADC12MSC| ADC12ON ; //Set S&H time = 16 CLK;
ADC12CTL1 = ADC12SHP|ADC12CONSEQ_1 ; // Sampling timer;Sequence mode;ADCCLK = MODCLK
ADC12CTL2 |= ADC12RES_2; // 12-bit conversion results
ADC12MCTL0 |= ADC12INCH_2 | ADC12VRSEL_1; // A2 ADC input select; Vref int
ADC12MCTL1 |= ADC12EOS_L| ADC12INCH_12 | ADC12VRSEL_1; // ADC12EOS_L : Set this channel as END OF SEQUENCE;A12 ADC input select; Vref
ADC12IER0 |= ADC12IE1; // Enable ADC conv complete interrupt just for the second and last channel
while(!(REFCTL0 & REFGENRDY)); // Wait for reference generator
__bis_SR_register(GIE); // ENABLE INTERRUPT
while(1)
{
}
return 0;
}
#pragma vector = TIMER0_A0_VECTOR
__interrupt void Timer0_A0_ISR (void)
{
ADC12CTL0 |= ADC12ENC | ADC12SC; // Sampling and conversion start
P1OUT |= BIT0;
}
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
{
switch(__even_in_range(ADC12IV, ADC12IV_ADC12RDYIFG))
{
case ADC12IV_NONE: break;
case ADC12IV_ADC12OVIFG: break;
case ADC12IV_ADC12TOVIFG: break;
case ADC12IV_ADC12HIIFG: break;
case ADC12IV_ADC12LOIFG: break;
case ADC12IV_ADC12INIFG: break;
case ADC12IV_ADC12IFG0: break;
case ADC12IV_ADC12IFG1:
ADC12CTL0 &= ~ ADC12ENC;
if(i<100)
{
ADC_A2[i]=ADC12MEM0;
ADC_A12[i]=ADC12MEM1;
i++;
P1OUT &= ~BIT0;
}
else
{
i=0;
}
break;
case ADC12IV_ADC12IFG2: break; // Vector 16: ADC12MEM2
case ADC12IV_ADC12IFG3: break; // Vector 18: ADC12MEM3
case ADC12IV_ADC12IFG4: break; // Vector 20: ADC12MEM4
case ADC12IV_ADC12IFG5: break; // Vector 22: ADC12MEM5
case ADC12IV_ADC12IFG6: break; // Vector 24: ADC12MEM6
case ADC12IV_ADC12IFG7: break; // Vector 26: ADC12MEM7
case ADC12IV_ADC12IFG8: break; // Vector 28: ADC12MEM8
case ADC12IV_ADC12IFG9: break; // Vector 30: ADC12MEM9
case ADC12IV_ADC12IFG10: break; // Vector 32: ADC12MEM10
case ADC12IV_ADC12IFG11: break; // Vector 34: ADC12MEM11
case ADC12IV_ADC12IFG12: break; // Vector 36: ADC12MEM12
case ADC12IV_ADC12IFG13: break; // Vector 38: ADC12MEM13
case ADC12IV_ADC12IFG14: break; // Vector 40: ADC12MEM14
case ADC12IV_ADC12IFG15: break; // Vector 42: ADC12MEM15
case ADC12IV_ADC12IFG16: break; // Vector 44: ADC12MEM16
case ADC12IV_ADC12IFG17: break; // Vector 46: ADC12MEM17
case ADC12IV_ADC12IFG18: break; // Vector 48: ADC12MEM18
case ADC12IV_ADC12IFG19: break; // Vector 50: ADC12MEM19
case ADC12IV_ADC12IFG20: break; // Vector 52: ADC12MEM20
case ADC12IV_ADC12IFG21: break; // Vector 54: ADC12MEM21
case ADC12IV_ADC12IFG22: break; // Vector 56: ADC12MEM22
case ADC12IV_ADC12IFG23: break; // Vector 58: ADC12MEM23
case ADC12IV_ADC12IFG24: break; // Vector 60: ADC12MEM24
case ADC12IV_ADC12IFG25: break; // Vector 62: ADC12MEM25
case ADC12IV_ADC12IFG26: break; // Vector 64: ADC12MEM26
case ADC12IV_ADC12IFG27: break; // Vector 66: ADC12MEM27
case ADC12IV_ADC12IFG28: break; // Vector 68: ADC12MEM28
case ADC12IV_ADC12IFG29: break; // Vector 70: ADC12MEM29
case ADC12IV_ADC12IFG30: break; // Vector 72: ADC12MEM30
case ADC12IV_ADC12IFG31: break; // Vector 74: ADC12MEM31
case ADC12IV_ADC12RDYIFG: break; // Vector 76: ADC12RDY
default: break;
}
}
