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Determining ADC sample/conversion time in clock cycles for MSP432P401r

Matthew Normyle
Prodigy 100 points


I need to be able to accurately estimate the sampling/conversion time for the ADC on the MSP432P401r, with the intent to run the ADC as fast as possible.


Since I am using 14bit samples, I know the conversion time will take 16 ADC_CLK cycles. However, I am lost as to how to accurately compute the sample time. The data sheet specifies a minimum of .215 microseconds, in addition to an 'at least 4 ADC_CLK cycles" specification.

If I am running the ADC clock at 48MHz, clearly 4 clock cycles is less than .215 microseconds. Should I adhere to the .215 microseconds specification?


Or should I simply use the knowledge that the maximum throughput is 1MSPS, and calculate the number of clock cycles for sample/conversion based on that?


Thanks!

  • 0
    TI__Guru**** 219337 points
    Hi Matthew,

    The amount of time the ADC14 requires to sample a signal depends on the ADC14SHT bits inside of control register ADC14CTL0. This value can be anywhere between 4 and 192 ADC14CLK cycles. This value in addition to the 16 ADC14CLK cycles required for conversion results in the total amount of time it takes for the ADC14 to sample & convert an analog input signal. Theoretically if ADC14CLK is sourced by a 48 MHz clock then it will take as little as 417 ns for sampling & conversion.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Prodigy 100 points
    Hi Ryan,
    Thanks for the response. The data sheet specifies the minimum time for a sample to be .215 microseconds. Clearly, 4 cycles of an ADCCLK running at 48MHz is less time than that.

    Is that an issue?
  • 0 in reply to Matthew Normyle
    TI__Guru**** 219337 points
    Hi Matthew,

    You are correct, I apologize for the confusion caused by my end. At 48 MHz both 4 & 8 ADC14CLK cycles is indeed less than 215 ns. You will have to use a ADC14SHT value of 3 or greater (>16 ADC14CLK cycles) to give the ADC14 time to properly sample the signal. Therefore the fastest sample & convert time you can achieve is (16 + 16)/48e6 = 667 ns or 1.5 MHz.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Intellectual 560 points

    Sorry if i introduce myself into the conversasion but my question is connected. If i set TimerA with smclk clock = 12MHZ and then i use divide fields to take it at 1Mhz then in adc fields i use adc14ssel = 4 (smclk), have i to divide adc14 clock (adc14div and adc14pdiv) to use 1 microsecond as adc14clock?

    Thanks

  • 0 in reply to Luca Palombella
    TI__Guru**** 219337 points
    If you are using the DIVS bits inside of the CSCTL1 register then the SMCLK output itself along with all sourced peripherals are reduced to the resulting frequency. The ADC14DIVx bits inside of the ADC14CTL0 register can then be used to further divide ADC14CLK. So if your SMCLK is 12 MHz then you can use DIVS = 2 to bring the SMLK frequency down to 3 MHz followed by ADC14DIVx = 2 to reduce ADC14CLK to 1 MHz.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Intellectual 560 points

    OK thanks :)
    Another question: how i decide che clock cycles of adc14? If i have 5us of time for repeated sequences of sampling/conversion how i calculate it? Starting the fact that the resolution of adc is 14bit (so 16 clock cycles of conversion) and the smclk = 12Mhz (it's the source clock of adc).

  • 0 in reply to Luca Palombella
    TI__Guru**** 219337 points
    As stated in the previous conversation: conversion cycles plus sample-and-hold cycles, divide that by clock frequency. 5 us times 12 MHz equals 60 cycles, subtract that by 16 conversion cycles and you have a maximum of 44 sample-and-hold cycles to work with.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Intellectual 560 points
    ok thanks :)
    Final question :p I don't understand utility of adc14msc: if i set ADC14SSEL_4 for source clock smclk , ADC14RES__14BIT for 14bit resolution, ADC14SHT0_3 to give Tsampling (what change if i set values higher or lower? if i am > 16 and <44 what change?) i am sure that values of adc are correct because it has time for make all sampling and conversion. But adc14msc? (i use conseq_2).
    Thanks,
    Luca
  • 0 in reply to Luca Palombella
    TI__Guru**** 219337 points
    Section 20.2.8.5 of the User's Guide states its purpose quite clearly, successive conversions are triggered automatically as soon as the prior conversion is completed to reduce time in between sample-and-conversion periods. It is recommended for repeat conversion functionality which you've described as desiring.

    The sample-and-hold time determines how many cycles the ADC will spend on sampling the signal before it is converted. Smaller values lead to quicker but less dependable/accurate results.

    Regards,
    Ryan

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