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MSP430F5659 PWM TA0.2 Register Confusion

k1mgy
Expert 1680 points
Other Parts Discussed in Thread: MSP430F5659

On the MSP430F5659 I wish to output a 1.6 KHz square wave on P1.7 (TA0.2).  I note that TA0.2 is assigned on P1.3 also, which is confusing (assuming asserting P1 SEL for the desired pin will assign it to the PWM output).


Using an ACLK of 32.768KHz, I create a timer/counter using these registers:

        P1DIR |= BIT7;                            // P3.5 output
        P1SEL |= BIT7;                            // P3.5 option select
        TA0CCTL2 = OUTMOD_4;                      // CCR0 toggle mode
        TA0CCR2 = 5;

TA0CTL = TASSEL_1 | MC_3 | TACLR;         // ACLK, up-downmode, clear TAR

This gives NO output.


However, (after experimenting) I found that this works:

        P1DIR |= BIT7;                            // P3.5 output
        P1SEL |= BIT7;                            // P3.5 option select
        TA0CCTL2 = OUTMOD_4;                      // CCR0 toggle mode
        TA0CCR0 = 5;

        TA0CTL = TASSEL_1 | MC_3 | TACLR;         // ACLK, up-downmode, clear TAR

How come?


Since the timer channel I am using is TA0.2 shouldn't the TA0CCR2 register be used?

Perhaps there is a simple chart that shows the association between each pin and the timer/counter registers, but I can't seem to find it.

Thank you.

  • 0
    Expert 1680 points
    From the User Guide I read the cryptic: "The output is set when the timer counts to the TAxCCRn value. It is reset when the timer counts to the TAxCCR0 value."

    I'm still trying to fully understand the relationship between these. For now, I suggest someone with a decent command of English revise the documentation. If the above were translated it might read, "In Set/Reset mode two registers are used, one to establish the frequency and the other to set the pulse width. "

    If the documentation were written more clearly, I bet these questions would not be necessary.
  • 0 in reply to k1mgy
    Guru 58965 points
    1) First about P1.3.

    Yes, P1.3 can also be used to deliver TA0.2 output (if it is not used for some other purpose).

    2) Next about your code that gave NO output.

    The problem here is you did not set TA0CCR0, hence it remains to be 0. And you set TA0CTL in the up-down mode, that means TA0R counts up to the value in TA0CCR0, and down to 0, and up to TA0CCR0, and down to 0, and up ... (repeat forever)

    Since TA0CCR0 is 0, this translate into count up to 0, down to 0, up to 0, down to 0, ...

    The result is, TA0R is not counting at all.

    3) About your code that works mysteriously.

    Here TA0CCR0 is set to 5. Thus TA0R counts up to 5, down to 0, up to 5, down to 0, ...

    The result is, it is actually counting!

    This time, you did not set up TA0CCR2, hence TA0CCR2 remains to be 0. This is okay.

    TA0CTL2 is set to toggle mode. Whenever TA0R matches TA0CCR2 (which is 0), TA0.2 (P1.7) toggles.
  • 0 in reply to old_cow_yellow
    Guru 58965 points
    BTW, most of the comments in your code are incorrect. But the compiler totally ignores all comments. Thus no harm done. Just looks bad!
  • 0 in reply to old_cow_yellow
    Expert 1680 points

    //most of the comments in your code are incorrect.

    Yes, I know.  Should have updated these.  Just cut and pasted without much edit.

    Thanks for the clearer explanation.

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