Byte order in MSP430F5x

All MSP430 families are compatible. The alignment requirements and endianness can be deduced from section 1.4.5 (Memory Organization) in the 2xx Family User's Guide:

Words are only located at even addresses as shown in Figure 1-3. When using word instructions, only even addresses may be used. The low byte of a word is always an even address. The high byte is at the next odd address.

The 5xx User's Guide does not mention anything about alignment, but the hardware has the same restriction.

Teh 'addressing modes' in chapter 6.4 cover the different ways of addressing a memory location, not the different data types when accessing a memory location :)
But you're right, the different data access mdoes aren't realyl covered, you can only indirectly learn about them.
When starting with MSP430, I mapped structures to a data stream without any alignment and was wondering why my code didn't work, even though analysis of the assembly code showed that everyhting shoudl be okay. Later I found a nice little sentence hidden deep in the MSPGCC compiler documentation: when using a word instruciton, the LSB is silently ignored by the CPU.

Any word access must be word aligned. Usually, the compiler takes care for this, but if you deliberately pass an odd pointer of a word-sized element to a function, results may be unpredictable. This is tricky when exchanging data structures with a processor that has random alignment (such as a PC)
As a result, I wrote a set of macrros that construct a word or dword value from an array of chars (which does not need alignment) and back.
The compilers have improved since, and when using a struct that is created with the packed attribute, the compiler always assumes possible misalignment and puzzles the values together from individual bytes.
Still passing a musaligned pointer of a word value to a function results in read/write access one byte lower than expected. With all bad resuslts this may bring.

Thanks a lot.
I see this information ror 2x family, but try to find OFICIAL information for 5x-6x series.

Thanks.
I think point "6.4 Addressing Modes" would be the best place in existing user guide for inserting note about MC alignment restictions, because there are address calculation for source and destination in every adressing modes. In those places could be writed something like "Attention! LSB of calculated addresses ignored! For correct word operation, operands should be have alignment 2". Or there should be separate point "alignment requirements of the MPU".
What you wrote about MSPGCC is good, but I asked slightly another:) For example, there are absolutly clear note about "ALIGNMENT ON THE MSP430 MICROCONTROLLER" in IAR compiler documentation, but it is documentation of third-party company. I try to find OFFICIAL information from MPU manufacturer, i.e. TI.
However thank for your story about problems with which you faced :)

When TI reorganized the CPU documentation, the information in the section "Memory Organization" was accidentally dropped. At the moment, there is no official information.

Thanks a lot for information.
One can only hope that nothing has changed in relation to series 2x and that the strict document will appear in the future.

"t the moment, there is no official information."

There is :)
Every CPU instruciton description that describes word access tells which emory addresses are accessed. So even though there currently is no explicit 'it is this way' statement, the info can be found.
Also, code written for the 2x family that handles byte/word mangling does still correctly work with the 5x family (and for 2x, the info is there). And there is of course no reason why providing a backwards compatible command set (sacrificing the 20bit benefits of the X core) and then going and changing endianess. Sometimes, engineers are no complete fools :) (well, sometimes, marketing or management orders them to act foolishly)