Setup: MSP430FR6989 LaunchPad, MCLK=8MHz, two UART modules configured for 115200, UART1 used for input, UART0 - for output, data is looped from UART0 to UART1 in an interrupt. All routines are reused from available examples.
Data transmission from MCU to PC at 115200 works as expected, test pattern 'U' comes with no error. At 57600 everything works as expected.
However, at 115200 and UART set up with recommended values:
UCA1BR0 = 4; UCA1BR1 = 0; UCA1MCTLW = 0x5500 | UCOS16 | UCBRF_5;
receiver reads 0x20 as 0x90 in ~ 50% cases.
This is an indication of the stop-bit read as the last bit.
The following combination gives similar results:
UCA1BR0 = 4; UCA1BR1 = 0; UCA1MCTLW = 0x0000 | UCOS16 | UCBRF_5; UCA1BR0 = 69; UCA1BR1 = 0; UCA1MCTLW = 0x0000;
The latter case should give bit error approx 6% that should be acceptable and should not produce strange readings.
With the following settings
UCA1BR0 = 67; UCA1BR1 = 0; UCA1MCTLW = 0x0000;
in 2% cases 0x20 is read as 0x30. Difference in byte duration for BR=67 and BR=69 is 2us, which makes 23%.
To exclude DCO errors I measured MCLK on P4.0 and readings where 8.00 MHz
Is there any explanation for this error?
My suspicion: receiver samples bits at the end of bit duration, not at the middle as it should
