Float points arithmetic on RAM MSP430F5438a

here is the DMA function:

unsigned char DMA_transfer(buffer *pointer_buffer) //DATA WRITE/PUSH
{
   int next = pointer_buffer->head + 1;
   if (next >= pointer_buffer->Num_Samples)
    next = 0;
   //buffer is full
    DMA0SZ =pointer_buffer->Num_Samples;
//    __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &d1);
    __data20_write_long((unsigned long) &DMA0SA,(unsigned long) & a);
    __data20_write_long((unsigned long) &DMA0DA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->head]);
	DMA0CTL |= DMAEN +DMAIE;                         // Enable DMA0
    DMA0CTL |= DMAREQ;                      // Trigger block transfer
    pointer_buffer->head = next;
    return 0;
}
void Uart_transfer(buffer *pointer_buffer)//DATA READ/POP
{
// if the head isn't ahead of the tail, we don't have any characters
 if (pointer_buffer->head == pointer_buffer->tail)
// return -1;  // quit with an error (buffer empty)
  DMA1SZ =pointer_buffer->Num_Samples;
  __data20_write_long((unsigned long) &DMA1SA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->tail]);
  __data20_write_long((unsigned long) &DMA1DA,(unsigned long) &UCA3TXBUF);
  DMA1CTL |= DMAEN; // // Enable DMA1
  DMA1CTL |= DMAREQ; // Trigger block transfer
  //pointer_buffer->buffer[pointer_buffer->tail]=0; //data remove from array location
  int next = pointer_buffer->tail + 1;
  if(next >= pointer_buffer->Num_Samples)
  next = 0;
  pointer_buffer->tail = next;

}

Suggestions are really apprecieted!!

Hi Dodz,

It's pretty hard to tell what you are trying to accomplish with the information given and the complexity of the DMA setup. Can you use the IDE debugger to confirm that the DMA registers are being written with the expected values? You could also try to see what the UART buffer is outputting to the serial monitor as compared to what it should be doing. I don't know what size transfers you are trying to accomplish but I notice that you never increment the source or destination inside of the DMAxCTL registers, which could be part of your issue. I would recommend reviewing the MSP430F5438A DMA code examples to get a better grasp of how to complete this task.

Regards,
Ryan

      void DMA_init()
      {  	  // Setup DMA0 double buffer
      	 DMACTL0 = DMA0TSEL_0;                    // Timer B triggered
                                                 // Read-modify-write disable
      	 DMA0CTL &= ~DMAIFG;
      	 DMA0CTL =  DMADT_5 +//a complete block transfer requires a trigger from Timer B
      			    DMASRCINCR_3 +//Source address unchanged
				    DMASRCBYTE +
					DMAIE +
					DMAEN +
      			    DMASBDB;//
      	 //DMA1 to UART
      	 DMACTL0 = DMA1TSEL_30; // DMA0 Trigger
      	 DMA1CTL = DMADT_5 +
      			  DMASRCINCR_3 +
      			  DMAEN +
      			  DMASBDB; //burst block transfer, inc src, enable

unsigned char DMA_transfer(buffer *pointer_buffer) //DATA WRITE/PUSH
{
	int next = pointer_buffer->head + 1;
   if (next >= pointer_buffer->Num_Samples+1)
    next = 0;
   //buffer is full
    DMA0SZ =pointer_buffer->Num_Samples;
//    __data20_write_long((unsigned short) &DMA0SA,(unsigned long) &d1);
//   __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &axg);
   __data20_write_long((unsigned long) &DMA0SA,(unsigned long) 0x001C26);
    __data20_write_long((unsigned long) &DMA0DA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->head]);
	DMA0CTL |= DMAEN;                         // Enable DMA0
//    DMA0CTL |= DMAREQ;                      // Trigger block transfer
    pointer_buffer->head = next;
    return 0;
}
unsigned char Uart_transfer(buffer *pointer_buffer)//DATA READ/POP
{
// if the head isn't ahead of the tail, we don't have any characters
 if (pointer_buffer->head == pointer_buffer->tail)
 return -1;  // quit with an error (buffer empty)
  DMA1SZ =pointer_buffer->Num_Samples;
  __data20_write_long((unsigned long) &DMA1SA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->tail]);
  __data20_write_long((unsigned long) &DMA1DA,(unsigned long) &UCA3TXBUF);
  DMA1CTL |= DMAEN; // // Enable DMA1
//  DMA1CTL |= DMAREQ; // Trigger block transfer
  //pointer_buffer->buffer[pointer_buffer->tail]=0; //data remove from array location
  int next = pointer_buffer->tail + 1;
  if(next >= pointer_buffer->Num_Samples+1)
  next = 0;
  pointer_buffer->tail = next;
  return 0;
}

#pragma vector=TIMER0_B0_VECTOR
__interrupt void TIMER0B0ISR(void)
{
//	DMA0CTL |= DMAEN;                         // Enable DMA0
    DMA0CTL |= DMAREQ;                      // Trigger block transfer
	overflow=1;
 __bic_SR_register_on_exit(CPUOFF);
}
#pragma vector = DMA_VECTOR
__interrupt void DMA_ISR(void)
{
DMA0CTL &= ~DMAIFG;
//DMA1CTL |= DMAEN; // // Enable DMA1
DMA1CTL |= DMAREQ; // Trigger block transfer
counter++;
	__bic_SR_register_on_exit(CPUOFF);
}

Hi Ryan, I decided to avoid float arithmetic, I switched to signed char to reduce complexity, the address of the var to print are

axg=0x001C25

ayg=0x001C26

azg=0x001C27

and I would like to get them printed in this order but when I read the buffer filled by the DMA I´m able to read

[ayg azg ayg] if start address is ayg

[0 axg 0] if the start address is axg

this is my dma setup(observing texas examples):

Hello Dodz,

Some notes on your DMA initialization:

1) There are TB0 DMA trigger assignments (DMAxTSEL_5 or DMAxTSEL_6) so that you don't have to enter a TB0 ISR. However you overwrite your original DMACTL0 assignment by using = instead of |= so the current setup works out in your favor...just an FYI in case you ever wanted to use the TB0 DMA trigger as it was intended.
2) The DMA ISR shouldn't be necessary since you set the DMA1 trigger select to DMA0IFG. I'm surprised that DMA1 is even being serviced.
3) Both DMASRCBYTE and DMASBDB are unnecessary for DMA0CTL and is most likely causing the register's result to be incorrect. Make sure that the DMAxCTL registers are as expected in your debugger.
4) What is DMAxSZ? It should be 3 since you are intending to send 3 bytes.
5) What are the values of axg, ayg, and azg in your example?

You're close to finding a solution but you will need to read the DMA chapter of the User's Guide and keep messing with your DMA settings until you find the correct match that sends the bytes correctly.

Regards,
Ryan

Thank you Rayan,
I checked the register and I tryed to solved the setup configurations as you suggested to me, I read the chapter on the user guide to check the setup
I wrote to differents setup I would like to follows yours because it seems to be more accurate but I wrote my working version that seems to be working. I will post both to know what do you think about that.
my message will be : 255 4 axg ayg azg 255 2 (where axg ayg azg are 8 bit values  0-255) Using the first version I´m still not getting the right message.

      void DMA_init()
      {  	  // Setup DMA0 double buffer
      	 DMACTL0 |= DMA0TSEL_6;                    // Timer B triggered
                                                 // Read-modify-write disable
      	 DMA0CTL &= ~DMAIFG;
      	 DMA0CTL |=  DMADT_5 +//a complete block transfer requires a trigger from Timer B
					DMAIE +
					DMAEN;//
      	 //DMA1 to UART
      	 DMACTL0 |= DMA1TSEL_30; // DMA0 Trigger
      	 DMA1CTL |= DMADT_5 +
      			  DMAEN;// +
      	 }
unsigned char DMA_transfer(volatile signed char *varadd, buffer *pointer_buffer) //DATA WRITE/PUSH
{
	int next = pointer_buffer->head + 1;
   if (next >= pointer_buffer->Num_Samples)
    next = 0;
   //buffer is full
    DMA0SZ =pointer_buffer->Num_Samples;
//   __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &ayg);
//   __data20_write_long((unsigned long) &DMA0SA,(unsigned long) varadd);
    if (pointer_buffer->head==0)
    	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &start[0]);
    if (pointer_buffer->head==1)
    	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &start[1]);
   if (pointer_buffer->head==2)
   	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &axg);
   if (pointer_buffer->head==3)
   	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &ayg);
   if (pointer_buffer->head==4)
   	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &azg);
   if (pointer_buffer->head==5)
   	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &stop[0]);
   if (pointer_buffer->head==6)
   	  __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &stop[1]);
    __data20_write_long((unsigned long) &DMA0DA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->head]);
    DMA0CTL |= DMAREQ;                      // Trigger block transfer
    pointer_buffer->head = next;
    return 0;
}

unsigned char Uart_transfer(buffer *pointer_buffer)//DATA READ/POP
{
// if the head isn't ahead of the tail, we don't have any characters
 if (pointer_buffer->head == pointer_buffer->tail)
 return -1;  // quit with an error (buffer empty)
  DMA1SZ =pointer_buffer->Num_Samples;
  __data20_write_long((unsigned long) &DMA1SA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->tail]);
  __data20_write_long((unsigned long) &DMA1DA,(unsigned long) &UCA3TXBUF);
  DMA1CTL |= DMAREQ; // Trigger block transfer
  //pointer_buffer->buffer[pointer_buffer->tail]=0; //data remove from array location
  int next = pointer_buffer->tail + 1;
  if(next >= pointer_buffer->Num_Samples)
  next = 0;
  pointer_buffer->tail = next;
  return 0;
}

#pragma vector=TIMER0_B0_VECTOR
__interrupt void TIMER0B0ISR(void)
{
	overflow=1;
 __bic_SR_register_on_exit(CPUOFF);
}
#pragma vector = DMA_VECTOR
__interrupt void DMA_ISR(void)
{
DMA0CTL &= ~DMAIFG;
counter++;
	__bic_SR_register_on_exit(CPUOFF);
}

 

while this is my working version:

unsigned char DMA_transfer(volatile signed char *varadd, buffer *pointer_buffer) //DATA WRITE/PUSH
{
int next = pointer_buffer->head + 1;
if (next >= pointer_buffer->Num_Samples)
next = 0;
//buffer is full
DMA0SZ =pointer_buffer->Num_Samples;
// __data20_write_long((unsigned long) &DMA0SA,(unsigned long) &ayg);
// __data20_write_long((unsigned long) &DMA0SA,(unsigned long) varadd);
if (pointer_buffer->head==0)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &start[0]);
if (pointer_buffer->head==1)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &start[1]);
if (pointer_buffer->head==2)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &axg);
if (pointer_buffer->head==3)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &ayg);
if (pointer_buffer->head==4)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &azg);
if (pointer_buffer->head==5)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &stop[0]);
if (pointer_buffer->head==6)
__data20_write_long((unsigned long) &DMA0SA,(unsigned long) &stop[1]);
__data20_write_long((unsigned long) &DMA0DA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->head]);
DMA0CTL |= DMAEN; // Enable DMA0
pointer_buffer->head = next;
return 0;
}
unsigned char Uart_transfer(buffer *pointer_buffer)//DATA READ/POP
{
// if the head isn't ahead of the tail, we don't have any characters
if (pointer_buffer->head == pointer_buffer->tail)
return -1; // quit with an error (buffer empty)
DMA1SZ =pointer_buffer->Num_Samples;
__data20_write_long((unsigned long) &DMA1SA,(unsigned long) &pointer_buffer->buffer[pointer_buffer->tail]);
__data20_write_long((unsigned long) &DMA1DA,(unsigned long) &UCA3TXBUF);
DMA1CTL |= DMAEN; // // Enable DMA1
//pointer_buffer->buffer[pointer_buffer->tail]=0; //data remove from array location
int next = pointer_buffer->tail + 1;
if(next >= pointer_buffer->Num_Samples)
next = 0;
pointer_buffer->tail = next;
return 0;
}

#pragma vector=TIMER0_B0_VECTOR
__interrupt void TIMER0B0ISR(void)
{
// DMA0CTL |= DMAEN; // Enable DMA0
DMA0CTL |= DMAREQ; // Trigger block transfer
overflow=1;
__bic_SR_register_on_exit(CPUOFF);
}
#pragma vector = DMA_VECTOR
__interrupt void DMA_ISR(void)
{
DMA0CTL &= ~DMAIFG;
//DMA1CTL |= DMAEN; // // Enable DMA1
DMA1CTL |= DMAREQ; // Trigger block transfer
counter++;
__bic_SR_register_on_exit(CPUOFF);
}

void DMA_init()
{ // Setup DMA0 double buffer
DMACTL0 = DMA0TSEL_0; // Timer B triggered
// Read-modify-write disable
DMA0CTL &= ~DMAIFG;
DMA0CTL = DMADT_5 +//a complete block transfer requires a trigger from Timer B
// DMASRCINCR_3 +//Source address unchanged
// DMASRCBYTE +
// DMADSTBYTE +
DMAIE +
DMAEN +
DMASBDB;//+
//DMA1 to UART
DMACTL0 = DMA1TSEL_30; // DMA0 Trigger
DMA1CTL = DMADT_5 +
DMAEN +
DMASBDB; //burst block transfer, inc src, enable
}