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MSP432 - clocking during exception (ISR)

Benjamin Bartsch
Prodigy 60 points


Hello,


in my application i want to sample any signal with the adc as fast as possible. I'm using the repeated sequence of channels mode and trigger the DMA with the ADC-exception (according to the ErrataSheet the trigger generated by the ADC14-Module does not work). This ISR was reduced to minimum functionality: 

- checking the source of the interrupt request (which flag was set)

- triggering the dma manually

- clear the flag

To check the timing of the interrupt and the maximum sample rate of my configurations, I toggled a pin at the begining and the end of the ISR. The Interrupt occurs continously, so I could easily analyze it with the oscilloscope. I wonderd how long it takes... Therefore I regarded the assembler code generated by CCS-IDE in the disassembly view. Considering the instruction set of the Cortex-M4 Technical Reference Manual, i counted the needed clock cycles. The result was, that it took nearly twice the number of time to process the ISR. How can that happend?

I aleady verified the core clock by mapping it to the appropiate output pin, and it was correct... 

  • 0
    TI__Mastermind 25045 points

    Hi Benjamin,

     Not sure if you are aware that you can configure a breakpoint as a counting event (in CCS). I've used it before and it gave me very accurate results. After you create a breakpoint, go into this breakpoint properties and configure it this way:

    And I'm measuring around 20 cycles in one example code that I have that uses the RTC ISR. Having said that, your interrupt latency will depend on your system (# of interrupts and priorities on these interrupts).

     So could you please share your expected clock cycles vs. what you are currently measuring.

      Thanks,

       David

  • 0 in reply to DavidL
    Prodigy 60 points

    Hi David,

    thanks for the answer! I've checked the clock cycles with this feature and the result is apropriate to the measured time. But nevertheless i don't understand the difference to the instruction set of the Cortex-M4 Technical Reference Manual. Are there any differences between the real number of clock cycles and the number specified in the instruction set?

    Here is a part of my ISR: 

    As you can see, the last command needed ten clock cycles. But when you count it according to the instruction set, it should be seven!
    In some cases the difference is bigger, so in the end the ISR needs 75 clock cylces instead of 38. That's a huge difference... ;-)

  • 0 in reply to Benjamin Bartsch
    TI__Mastermind 25045 points
    Hi Benjamin,

    A couple of weeks ago, I went thru the same exercise "trying to match the instruction cycles with the Cortex-M4 Technical Reference Manual" and it was not that easy. You will have to understand how the instructions are being feed into the pipeline (debugging in assembly + using the clock cycles in CCS).

    Also you may want to enable optimization to improve your code performance.

    Best regards,

    David
  • 0 in reply to DavidL
    Prodigy 60 points

    Hi David,


    as i remember the pipelining will be done with loading and storing instructions. But honestly i did't read the whole Cortex-M4 Manual, so probably i'm not aware of any important information... ;-)

    Nevertheless, i was able to reduce the clock cycles by the Optimization-Tool, like you suggested. So the application works with the doubled sample rate. Unfotunately, the first time I tried to use the Optimization, however, the floating point operations didn't work anymore. Maybe the problem was, that i didn't cleaned the project before, I just builded it with the changed Optimization-settings.

    So thanks for your support!


    Best regards

    Benjamin

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