error, change system clock to external clock signal

sorry for lose the test code which is below:

void MCU_Init()
{
UCSCTL6 = XT1BYPASS|XTS|XT1OFF|XT2OFF ; /*changed to external clock signal*/
UCSCTL5 |= (DIVA__2|DIVS__4|DIVM__1); /*ACLK,SCLK,MCLK division*/
UCSCTL4 &= ~(SELA_7|SELS_7|SELM_7); /*Set ACLK = XT1,SCLK = XT1,MCLK = XT1*/

/* Loop until XT1,XT2 & DCO fault flag is cleared*/
do
{
UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG);/* Clear XT2,XT1,DCO fault flags*/
SFRIFG1 &= ~OFIFG; /* Clear fault flags*/
}while (SFRIFG1&OFIFG); /* Test oscillator fault fl*/
}
(Note: XT1HFOFFG is setting always and lasts ~1.25ms)

The User's Guide says:

Fault logic counters

Each crystal oscillator circuit has hardware counters. These counters are reset each time a fault condition occurs on its respective oscillator, causing the fault flag to be set. The counters begin to count after the fault condition is removed. When the maximum count is reached, the fault flag is removed.

In XT1 LF mode, the maximum count is 8192. In XT1 HF mode (and XT2 when available), the maximum count is 1024. In bypass modes, regardless of LF or HF settings, the maximum count is 8192.

At 6 MHz, 8192 cycles is 1.37 ms.

Hi Ladisch,

Thank you for your infor.

I nearly pay no attention to the fault counter. It seems right as the count 8192,but why takes 6MHz not 1.04M to get the duration? As mentioned before, the MCLK runs on the default clock which is ~1.04MHz while XT1HFOFFG keeps setting.

Those counters count cycles of the input clock.

Hi Ladisch,

could you clear me the doubt again?

I raise the question 1 year ago referred to the case that while switching the MCLK from internal osc to external osc in which I found the XT1HFOFFG flag will be set and last 1.25ms even though the external oscillator has been stable. I review it today and have a doubt that is it necessary to clear the XT1HFOFFG while switching the MCLK clock? I mean, should I switch the MCLK to external osc immediately without waiting for the XT1HFOFFG is clear because the external osc is already stable.

Also, I'm not clear for the setting of XT1HFOFFG in this case. In my opinion the XT1HFOFFG is set just for clock synchronization as showed below in user's guide, am I right?

 

Clock synchronization happens only when the new clock is valid, i.e., only when the fault counter has expired.

As long as you do not clear XT1HFOFFG, the new clock source will not actually be used.