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MSP430FR6989 Crystal Clock could not get to work

Haizhen Zhou
Prodigy 110 points
Other Parts Discussed in Thread: MSP430FR6989

I followed code example msp430fr69xx_cs_04 for 16MHz crystal configuration. The OFIFG flag is always set and the system stopped at the do loop.

I changed the crystal to 8MHz, the problem is the same.

Change the clock to DCO configuration, the system works fine. 

Here is the code:

WDTCTL = WDTPW | WDTHOLD; // Stop WDT

// GPIO Setup
P1OUT = 0;
P1DIR = BIT0; // For LED

PM5CTL0 &= ~LOCKLPM5;
FRCTL0 =0xA570;
// Set up HXT1

// Clock System Setup

PJSEL0 |= BIT6 | BIT7; //For HXT2
CSCTL0_H = CSKEY >> 8; // Unlock CS registers
 // Set DCO to 8MHz
CSCTL1 = DCOFSEL_6;

CSCTL2 = SELA__VLOCLK | SELS__HFXTCLK | SELM__HFXTCLK;
CSCTL3 = DIVA__1 | DIVS_2 | DIVM__2; // Set all dividers
CSCTL4 |= HFXTDRIVE_3 | HFFREQ_2;
CSCTL4 &=~HFXTOFF;
do
{

CSCTL5 &=~HFXTOFFG; // Clear HXT2 fault flag
SFRIFG1 &= ~OFIFG;

} while (SFRIFG1 & OFIFG); // Test oscillator fault flag

CSCTL0_H = 0; // Lock CS registers

Please tell me What is the problem?

  • 0
    Guru 317370 points
    Show your circuit.
  • 0 in reply to Haizhen Zhou
    Prodigy 110 points
    Please help to check why the crystal is not working.
    Thanks
  • 0 in reply to Haizhen Zhou
    TI__Guru**** 217857 points
    PJSEL0 |= BIT6 | BIT7; needs to come before PM5CTL0 &= ~LOCKLPM5; or else port J will never be initialized correctly and HFXT will never oscillate, resulting in the OFIFG flag not clearing.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Prodigy 110 points

    Hi, Ryan,

    I tried. It does not work. Here is the code. Please advise.

    #include <msp430fr6989.h>

    /*
     * main.c
     */
    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
        // Configure GPIO
        P3DIR |=BIT7;  //LED R
        P6DIR |=BIT4;  //Hardware WDT
        P4DIR |=BIT0+BIT1;     //LED G Y

       


        PJSEL0 |= BIT6 | BIT7;      // For XT2

        // Disable the GPIO power-on default high-impedance mode to activate
        // previously configured port settings
        PM5CTL0 &= ~LOCKLPM5;

        FRCTL0 =0xA570;

        CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers
        CSCTL1 = DCOFSEL_6;                       // Set DCO to 8MHz
        CSCTL1 =DCORSEL + DCOFSEL_4;                        // Set DCO to 16MHz
       // CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;

        CSCTL2 = SELA__VLOCLK | SELS__HFXTCLK | SELM__DCOCLK;
        CSCTL3 = DIVA__1 | DIVS__2 | DIVM__1;     // Set all dividers to 1
        CSCTL4 |=  HFXTDRIVE_3;
        CSCTL4 &= ~(HFXTOFF);
        do
        {
          CSCTL5 &= ~(HFXTOFFG);       // Clear XT2 fault flag
          SFRIFG1 &= ~OFIFG;
        }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

        CSCTL0_H = 0;

        P6OUT &=~BIT4;

        while(1)
        {
           __delay_cycles(8000000);                // Wait 8,000,000 CPU Cycles

             P3OUT ^=BIT7;   //LED
              P4OUT ^=BIT1;
              P4OUT ^=BIT0;

           P6OUT |=BIT4;
           __delay_cycles(16000);
           P6OUT &=~BIT4;

        }

     return 0;
    }

  • 0 in reply to Haizhen Zhou
    Guru 58965 points
    Your PCB layout at and near the Crystal needs to be checked by an experienced hardware engineer. Your TEST POINT there is uncalled for.
  • 0 in reply to Haizhen Zhou
    TI__Guru**** 217857 points
    For debugging purposes, please change the MCLK and SMCLK configurations to DCO and only leave ACLK as sourced by the HFXTCLK. Then output ACLK on pin 5.2. Are you able to see an oscillation on the pin? You could also use an o-scope probe to make sure that the crystal itself is oscillating properly. This will determine whether the problem lies with the crystal hardware or the firmware setup/initialization. Most high-frequency crystals use smaller parallel capacitance values, can you please tell us exactly which crystal you are using? Also, as OCY mentioned, it might help if you are able to show us your board layout.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Prodigy 110 points

    Ryan,

    It seems to me that ACLK could not source HFXCLK with the control register CSCTL2. SELA can only be sourced by LFXTCLK, VLOCLK and LFMODCLK. I checked with oscilloscope that the crystal was oscillating when the code hanging at While check loop while (SFRIFG1&OFIFG); The Part number for The crystal is ECS-160-20-5PXDU-TR. I will show you the PCB layout latter.

    Regards,

    Albert

  • 0 in reply to Haizhen Zhou
    TI__Guru**** 217857 points
    You are correct about ACLK, please try sourcing only the SMCLK with HFXTCLK instead and output SMCLK on one of its available pins. However the fact that your code hangs while testing the oscillator fault flag proves that the issues lies with your crystal hardware. The design itself is not recommended since it uses vias to place crystal on the opposite side (and even underneath) of the MCU. The test point is unnecessary and there are also several digital communication lines which run very close to and underneath the crystal which is not a good idea. The load capacitance is 20 pF so your parallel capacitors should be 30 to 36 pF using the equation C1,C2 = 2*(CL-Cstray) where Cstray is stray capacitance that usually falls within the range of 2 to 5 pF.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Prodigy 110 points
    Ryan,
    Yes, I tried using SMCK with HFXTCLK as source. the crystal voltage waveform is stable at XOUT of 16MHz 1Vpp(PJ7) and 0.8Vpp at XIN(PJ.6) . I will replace the 20pF cap to 30pF -36pF as your suggested.
    Thanks.

    Albert
  • 0 in reply to Ryan Brown1
    Prodigy 110 points
    Ryan,
    I have changed the cap 20pF to 35pF by piggyback a 15pF cap. The result is the same. The oscillation of the crystal seems fine. HFXin signal is 16MHz sinewave with Vpp of 0.75V and HFXOUT signal is 1.0Vpp. However, the oscillator fault flag can not be cleared.
  • 0 in reply to Haizhen Zhou
    Guru 317370 points

    The cs_04 example uses both LFXT and HFXT.

    I'd guess that LFXTOFFG is set the entire time, and thus forces OFIFG on. (As far as I can see, you have correctly configured the module to not use LFXT, but this doesn't help if LFXTOFFG is already set.)

    Try clearing this flag, too.

  • 0 in reply to Clemens Ladisch
    Prodigy 60 points

    Ryan,

    I added LFXTOFFG to CSCTL5 &=~(LFXTOFFG |HFXTOFFG). 

    It works!  

    A great lesson for me.

    Thank you so much!!!

    Albert Zhou

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