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SMCLK frequency in MSP432

Otavio Augusto Gomes
Intellectual 940 points

Hello:

I have a question about SMCLK maximum frequency. I was setting the Clock System of my MSP432 when I came across with the following statement in the MSP432 User Guide (SLAU356A, page 292):

SMCLK uses the HSMCLK clock resource selection for its clock resource... SMCLK is limited in frequency to half of the rated maximum frequency of HSMCLK.

But, by checking the Clock System diagram in the same user guide (page 293):

I can't understand that limitation, once the clock source is the same, as indicated by the red arrow, both for HSMCLK and SMCLK. What provides the referred limitation? It would be helpful to obtain further explanations about it.

Thanks!

  • 0
    Guru 92251 points

    Looking at the MSP432P401R datasheet SLAS826A, shows that the maximum SMCLK input frequency for the eUSCI and Timer_A peripherals is 24MHz. Where 24MHz is half the maximum 48MHz for the MSP432 Clock System.

    Maybe that explains the SMCLK limitation.

  • 0 in reply to Chester Gillon
    Intellectual 940 points

    OK, but my question is related to SMCLK relative to HSMCLK and not relative to maximum rated frequence of MSP432 clock system. The statement of user guide is:

    "SMCLK is limited in frequency to half of the rated maximum frequency of HSMCLK.

    But, for me, this statement does not seem to correspond with the diagram shown above.

  • 0 in reply to Otavio Augusto Gomes
    Guru 92251 points

    Otavio Augusto Gomes said:
    But, for me, this statement does not seem to correspond with the diagram shown above.

    The diagram shows the different possible options for generating SMCLK and HSMCLK, in which the generated SMCLK and HSMCLK may be the same or different frequencies, depending upon the value of the DIVS and DIVHS clock divisor selections.

    It depends upon the frequency of the clock source selected by the SELS bits about if SMCLK must be limited in frequency. This is because the maximum allowed frequency for SMCLK is 24 MHz, due to which peripherals which SMCLK provides the clock for. E.g.:

    - If the SELS bits select a 24 MHz clock source, then SMCLK and HSMCLK may both be 24 MHz (both DIVS and DIVHS select  divide-by-1).

    - If the SELS bits select a 48 MHz clock source, then HSMCLK may be 48 MHz (DIVHS selects divide-by-1), but SMCLK must be a maximum of of 24 MHz (DIVS selects divide-by-2).

    Maybe the documentation could be clarified over this.

    SMCLK can source the clock for all peripherals apart from ADC14, whereas ADC14 can have its clock sourced from SMCLK or HSMCLK (among others).

  • 0 in reply to Chester Gillon
    Intellectual 940 points

    I agree. In this case, I think that the SMCLK is not self-limited, and the user software must selects the proper value for DIVS, right?

  • 0 in reply to Otavio Augusto Gomes
    Guru 92251 points

    Otavio Augusto Gomes said:
    In this case, I think that the SMCLK is not self-limited, and the user software must selects the proper value for DIVS, right?

    Yes, that is my understanding based upon reading the MSP432 datasheet and user's guide.

  • 0 in reply to Chester Gillon
    Guru 74080 points
    This is my understanding as well.

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