Hi!
I utilize the code provided in MSP430x5xx Family User Guide section 2.2.4 to increase the VCORE voltage. However, I have found out that the delays do obviously not work but are simply overridden - I don't find another reason.
For instance, I run the MCLK at 8MHz from the DCO, increase the VCORE step by step and then get back to VCORE=0. Starting from VCORE=0 at 1.43V a slope can be found which ends 35µs later at about 1.62V - this is practically the minimum number of MCLK code instruction cycles for 3 increases with 8MHz. Btw: If I include a delay of >=100us after the VCORE change the voltage goes to its final value as expected and provided in the datasheet. Each step then takes about 100µs (470nF cap, VCC=3V) until the plateau is reached.
Obviously the delay flag for SVM does not work (I included a counter register in the loops and there were practically no counts).
One thing that I tried out was to use the SVSMLDLYST flag in the SVSMLCTL register rather than the SVSMLDLYIFG in PMMIFG. Guess what happens? Just polling that flag causes a system reset. WTF how can that happen?
You can find the code below - sorry, it's a little bit hard-core assembler for faster processing and reduced code size ;)
L_SYS_IncVCore:
mov &PMMCTL0,R12 // { Get actual VCORE.
and #3,R12 // }
inc R12 // 1 Set to new value
bit #BIT4,R12 // 1 already overflow to 3rd bit?
jnz IncVCore_End // 2 If yes, then VCORE=3 already given
mov.b #0xA5,PMMCTL0_H // 4 Open PMM registers for write access
IncVCore_Lp0: bit #SVSMHDLYIFG,&PMMIFG // 4 SVS/SVM high-side delay expired?
jz IncVCore_Lp0 // 2
IncVCore_Lp1: bit #SVSMLDLYIFG,&PMMIFG // 3 SVS/SVM low-side delay expired?
jz IncVCore_Lp1 // 2
mov &SVSMHCTL,R13 // 3 { Modify SVS/SVM for High side
bis #SVSHE+SVMHE,R13 // 2 ..
bic #0x0307,R13 // 2 ..
add R12,R13 // 1 ..
swpb R12 // 1 ..
add R12,R13 // 1 ..
mov R13,&SVSMHCTL // 3 }
mov &SVSMLCTL,R13 // 3 { Modify SVM (not SVS!) for Low Side
bis #SVSLE+SVMLE,R13 // 2 ..
bic #0x0307,R13 // 2 ..
sub #SVSLRVL0,R12 // 1 .. Keep SVSLRVL on old level
add R12,R13 // 1 ..
swpb R12 // 1 ..
inc R12 // 1 ..
add R12,R13 // 1 ..
mov R13,&SVSMLCTL // 3 }
//IncVCore_LpX: bit #SVSMLDLYST,&SVSMLCTL // Using this loop rather than the next one
// jc IncVCore_LpX // causes resets & undefined behaviour.
IncVCore_Lp2: bit #SVSMLDLYIFG,&PMMIFG // 3 Wait till SVM is settled
jz IncVCore_Lp2 // 2
bic #SVMLVLRIFG + SVMLIFG,&PMMIFG // 5 Clear already set flags
mov.b R12,&PMMCTL0_L // 4 Set VCore to new level
bit #SVMLIFG,&PMMIFG // 3
jz IncVCore_Jmp0 // 2
IncVCore_Lp3: bit #SVMLVLRIFG,&PMMIFG // 4 Wait till new level reached
jz IncVCore_Lp3 // 2
IncVCore_Jmp0: add.b #SVSLRVL0_H,&SVSMLCTL_H // Set SVSLRVL to new (higher) level
mov.b #0,&PMMCTL0_H // 3 Lock PMM registers
IncVCore_End: ret // 4
