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What is FCLK in MSP432?

Julian Kolodko
Expert 2265 points


G'Day all,

What is FCLK?


SLAU356A describes it as a "free running clock", but does not describe it's relationship to all the other clocks in the device.
SLAU356A mentions it twice - once WRT SYSTICK, and once WRT the SLEEPCNT register.
SLAS826A doesn't mention it at all.


I'm guessing it is the same as MCLK, but I'd appreciate confirmation.

BTW, I tried raising this question via the "Submit Documentation Feedback link" at the bottom of SLAU356A

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLAU356A#

but I get an "Internal Server Error" when I click the submit button.

Cheers

Julian

  • 0
    TI__Guru**** 219477 points
    G'Day Julian,

    FCLK refers to the CPU clock speed. MCLK is used by the CPU but it is not equivalent to FCLK. The maximum CPU operating frequency is 48 MHz and maximum input clock frequency for peripherals is 24 MHz (during AM_LDO_VCORE1 or AM_DCDC_VCORE1 modes). The CPU is on during active modes and off while in LPMs.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Expert 2265 points

    G'Day Ryan,

    Thanks for that info, but I'm still a bit confused.

    Is there any formal documentation regarding FCLK?

    E.g. What is the source of FCLK? Can FCLK be configured in any way?  What is the relationship between FCLK and MCLK.  What does FCLK do in LPM modes?  Is the CYCCNT registers associated with FCLK (I already know the SYSTICK register runs from FCLK)?

    Cheers

    Julian 

  • 0 in reply to Julian Kolodko
    TI__Guru**** 219477 points

    G'Day Julian,

    I'm sorry that my previous post did not make the matter clear enough. FCLK = CPU clock speed which is sourced by MCLK, therefore MCLK and FCLK share the same frequency (dependent on MCLK configuration). The main difference is that MCLK can be still active in LPM0 whereas FCLK (CPU) is turned off. For all other LPMs both are turned off. SYSTICK and CYCCNT are sourced by FCLK because they count active PC cycles.

    Regards,
    Ryan

  • 0 in reply to Ryan Brown1
    Prodigy 70 points

    Could you clarify something about this with respect to SysTick?  

    There is an example, systick_interrupt_gpio_blink.c, for MSP432 DriverLib which uses a SysTick ISR to periodically wake from LPM0 and blink an LED.  If SysTick is sourced from FCLK, and FCLK is turned off in LPM0, how does the periodic wake-up work?  

    Thanks, 

    John

  • 0 in reply to John Pitney
    TI__Guru**** 219477 points
    Hello John,

    Thank you for bringing up this example that clearly shows SysTick being sourced from MCLK. My confusion came from the STCSR register section of the User's Guide which indicated that SysTick would be sourced from the core clock, which I believe is turned off in any LPM according to Table 7-1. I will confer with the design team for clarification on this issue.

    Regards,
    Ryan
  • 0 in reply to Ryan Brown1
    Expert 2265 points
    G'Day Ryan,

    Have you managed to get any further information?

    I don't see the core clock specifically mentioned in that table, but by my reading, for LPM0 in any of the LDO/DCDC modes
    * All clocks (low and high frequency) can be active
    * CPU is inactive.

    So, is FCLK a clock that can remain active, or is it a part of the CPU itself which is inactive?
    Since the example works, I'm guessing its the former????

    Cheers
    Julian
  • 0 in reply to Julian Kolodko
    TI__Intellectual 960 points
    Julian,

    Let me clarify the clock scheme in MSP432.

    1) MCLK, SMCLK and ACLK are the system clocks.
    2) MCLK sources FCLK which is a free running clock for the core (The core includes CPU, MPU, FPU, JTAG, SYSTICK etc)
    3) FCLK sources multiple internal clocks (including cpuclk, HCLK, PCLK etc) which are gated clocks used for parts of the core (including CPU), and other peripherals.

    In LPM0, the cpu clock is gated and CPU is put to sleep mode.
    But FCLK remains active and hence Systick can remain active as well.

    In short, the cpu's clock, FCLK, MCLK are all the same, except that they are gated/stopped for different conditions.

    Regards,
    Venu
  • 0 in reply to Venu S
    Expert 2265 points
    Hi Venu,

    Thank your for you feedback!
    You've pretty much covered it.
    Is there a document that describes all these clocks and their gating conditions?
    It might save me from posting similar questions here in future.

    The one outstanding question I now have is related to HCLK/Timer32 (I tried to ask in another thread but was asked to bring the question back into this thread)

    Does Timer32 (which runs from HCLK) continue to run in LPM0.

    Cheers
    Julian

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