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Flash memory controller in MSP430F149

John J Wu
Genius 3870 points
Other Parts Discussed in Thread: MSP430F149

I have some questions regarding the MSP430F149 Flash Memory Controller.

Section 5.3.5 of slau049e, “Stopping a Write or Erase Cycle”, states that on using the emergency exit “the result of the intended operation is unpredictable”

Is this unpredictable result of emergency exit more desirable than any result of a reset during a write / erase operation?

Section 5.3.1 of slau049e, pg. 39 of slas272f, specifies the flash timing generator operating frequency, fFTG, must be in the range from 257 kHz to 476 kHz.

Do you have any suggestions for verifying flash operating frequency (can one see it on an I/O pin)?

Thanks a lot.

  • 0
    TI__Mastermind 24390 points

    Arrow Vancouver said:
    Section 5.3.1 of slau049e, pg. 39 of slas272f, specifies the flash timing generator operating frequency, fFTG, must be in the range from 257 kHz to 476 kHz.
    Do you have any suggestions for verifying flash operating frequency (can one see it on an I/O pin)?
    Thanks a lot.

    You can't bring the flash timing generator frequency to a pin directly, but you can ouptut it's source clock (SMCLK, MCLK, ACLK) to a dedicated clock output pin. fFTG consists of a clock source and divider settings. The only element you would ever need to monitor would be the stability of the clock source, so using pins 48, 49, or 50 should help.

    I'm not sure about the first part of the question. Perhaps someone else can comment.

  • 0
    Guru 227245 points

    Unpredictable means that the data may or may not have been written properly. Some bits may, some may not and maybe the data will start to give unstable results after a minute, a day or a year.

    The outcome when a reset occurs may be the same, bu tif you do an emergency exit, you might be able to repeat the operation later after handling the emergency situation. (e.g. you need to handle an interrupt immediately - a collision alarm in a car, airbag triggering etc. - and need to stop the writing process so you can execute the ISR in flash, but then can try again).

    The newer MSPs flash controlelrs have a margin scan option that allows to check the result of a write or erase operation by disabling the flashs internal schmitt-triggers, so you can detect possibly unstable bits even if they are correctly read under normal cicumstances (yet). This scan must be performed from ram, as any opcode fetch from flash will disable it.

    If the flash operating frequency is too high or too low, writing might fail too. You can check this with the margin scan too, but then, those MSPs with a flash controller with margin scan have an internal oscillator for the timing and are not sourced by a user-controllable clock anyway.

    On the older ones, the way to check is to output the clock source (e.g. SMCLK) and measure it and do some math (flash clock divider).

    On a self-contained system, there's no way to to do a frequency self-check. Since the MSP does not know the frequency of its frequency reference. You'll need an external calibrated measuring equipment or at least a verified calibrated external clock source to do any checking.

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