MSP430F5529 LF XT1 runs fine at 32768, but can't clear XT1LFOFFG

This is a board of our own design, based on the 5529 LaunchPad. It is a slight variation of an older board which works fine. I wonder what could cause the XT1LFOFFG  to continually go high even though the MCU P1.0 sends out a nice 32KHz square wave. 

The code is just the example code from the CCS resource explorer. It stays in the do loop that is supposed to allow XT1 to settle.

#include <msp430.h>

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

P1DIR |= BIT0; // ACLK set out to pin
P1SEL |= BIT0;
P5SEL |= BIT4+BIT5; // Select XT1

UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 = 0; // FLL Reference Clock = XT1
PJDIR =0xF;
PJOUT = BIT0;

// OFIE

// Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
PJOUT = BIT2;

UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength

UCSCTL4 |= SELA_0; // ACLK = LFTX1 (by default)

__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}

Section 5.2.12 of the User's Guide says:

If ACLK is sourced from XT1 in LF mode, an oscillator fault causes ACLK to be automatically switched to the REFO for its clock source (REFOCLK).

And REFO also runs at 32.768 Hz, only with less precision.

What is that "slight variation"? Or the crystal/soldering could be bad.

If you don't notice the difference, why have the crystal in the first place? ;-)

Anyway, you can detect REFO being used only with the XT1LFOFFG bit (or the NMI, if enabled).

Solved! We have two crystals: 32 kHz and 24 MHz, The assembly house reversed them. Not understanding how REFO worked had me looking in the wring places. Thanks Clemens for the explanation.