Reading a wrong byte in the SPI Rx Buffer

Hi Viney!

Everytime I see anyone having problems with ADSxxxx ADC's from TI, my first question is about the configuration of the SPI module. You do not show the code and I cannot clearly see this in the scope screens, but did you configure the SPI module to latch the data on the falling edge of CLK, not on the rising? This is a mistake that is made quite often because in most cases data is latched on the rising edge. Just to make sure the problem isn't caused by this wrong bit setting.

Dennis

An incorrect SPI mode (CPOL/CPHA) wouldn't necessarily (visibly) affect all bytes, since what you're reading is transitional states -- rise/fall times, pin capacitance and the like.

When faced with mysterious SPI failures and/or indecipherable spec sheet descriptions, I usually fall back on ("last refuge of scoundrels"):

1) Try all the SPI modes in turn -- there are only 4 of them.

2) Slow down the SPI until something changes, or at least until it's so slow it get silly.

These of course aren't a cure, but rather a diagnosis path.

My experience with SD cards is that they're (a) all different, at least in the corner cases, and (b) all finicky.

Nitesh,

You need to first set the UCB0CTL1  bit 0 to 1 before making any change to UCB0CTLx

UCB0CTL1 |= UCSWRST

UCB0CTL0 |= UCMST+UCSYNC+UCMSB;

UCB0CTL1 |= UCSSEL__ACLK; // ACLK

UCB0BR0 = 24; // 1 MHz

UCB0BR1 = 0; //

UCB0CTL1 &= ~UCSWRST

You need to add the two lines highlighted in green.

If the UCB0TL1 bit 0 is not set to 1 the changes can not be made and hence the change would not be registered and this bit after the change the bit needs to be set back to 0.

What is the clock source for the ADS1292, internal or external, if external then @ what speed, While writing the registers there is a limit on SCLK speed but @1MHz the SCLK speed should be ok for register read/Write even if you consider 512 kHz for the internl clock.

Moreover the MCLK speed is 4 MHz or 24 MHz, is the @4MHz a typo or you want to say the system runs at 4 MHz,

"System runs @4Mhz and i am using ACLK for SPI,"

In case the system speed is 24MHz then the ACLK with the divisor as 24 would run at 1 MHz.

Regards

Viney Chaddha

Hi Viney,

Thanks for the reply. i am able to read the ADC count from ADS1292 channel 2 using 1Mhz SPI clock. ADS1292 has internal clock of 500KHz and sampling @ 500SPS.

My only problem is i am seeing some drift in my ADC count.

Here is our formula for calculating the ADC converted data for positive range.

                                     Voltage measured Value  =  Vref (2.42v)/ (2^23-1) * ADC Count (23 bit considered ignoring MSB 24bit if set)

For Ex.

                0.8v  input value, measured count  0x23EE91 after calculation measured voltage is – 0.67v while expected value was 0x2A5065 counts

0.4v  input value, measured count 0x11CbD4  after calculation measured voltage is – 0.336v while expected value was 0x152832 counts

And we are seeing constant linear drop in measured value.

I would appreciate you, if you can help in solving this issue.

Thanks,

Nitesh 

Hi Viney,

Thanks,

I have done few experiments on channel 2 where we are giving the differential input which was suggested by our direct TI focal person.

1. Channel 2 gain set to 1.

2. Channel 2 input shorted by setting 001, and measured offset.  Read offset value is 13E (318.668)  

3. Channel 2 input set to MVDD for measure power supply by setting 011. Read ADC count value is 13E (318.588). This value is almost equal to the offset value, instead of VDD/4 (3.3/4 = 0.825 v)

i felt MVDD differential input is almost zero.

This was not helped us. Will try as per your input and i will let you know the observations.

Thanks,

Nitesh