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I get faultISR with BackChannel UART and ADC14 using driverlib and MSP432. How to debug?

Rob Frohne
Expert 1505 points
Other Parts Discussed in Thread: CCSTUDIO

Hi,

I combined two examples, one from MSPWare (using the ADC14 in to measure several things), and the other was the Backchannel UART .  Each works fine alone, but when I put the two together, I end up after the first printf() at faultISR().  Here are my main.c, and the printOverride.c, and the startup.c files.  I would appreciate any ideas on how to find what might be happening.

Thanks,

Rob

/******************************************************************************
 * 2016 WWU Direct Conversion VNA
 * Author: Rob Frohne
 * Thanks to Gerard Sequeira, 43oh for the backchannel UART ideas and to TI for
 * the examples and driverlib.
*******************************************************************************/
#define USE_SPI
/* DriverLib Includes */
#include "driverlib.h"
#include "msp432.h"
#include "hw_memmap.h"
/* Standard Includes */
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
/* Global variables */
void initializeClocks(void);
int initializeBackChannelUART(void);
int initializeADC(void);
const eUSCI_UART_Config uartConfig =
{
        EUSCI_A_UART_CLOCKSOURCE_SMCLK,          // SMCLK Clock Source
        26,                                      // BRDIV = 26
        0,                                       // UCxBRF = 0
        0,                                       // UCxBRS = 0
        EUSCI_A_UART_NO_PARITY,                  // No Parity
        EUSCI_A_UART_LSB_FIRST,                  // MSB First
        EUSCI_A_UART_ONE_STOP_BIT,               // One stop bit
        EUSCI_A_UART_MODE,                       // UART mode
        EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION  // Low Frequency Mode
};
#define NUM_ADC14_CHANNELS 4
/* Results buffer for ADC14 */
uint16_t resultsBuffer[NUM_ADC14_CHANNELS]={0,0,0,0}; //ADC results
/*
 * This interrupt is fired whenever a conversion is completed and placed in
 * ADC_MEM7. This signals the end of conversion and the results array is
 * grabbed and placed in resultsBuffer
 */
void ADC14_IRQHandler(void)
{
    uint64_t status;
    status = ADC14_getEnabledInterruptStatus();
    ADC14_clearInterruptFlag(status);
    if(status & ADC_INT3)
    {
        ADC14_getMultiSequenceResult(resultsBuffer);
    }
}
/*
 * USCIA0 interrupt handler for backchannel UART.
 * For interrupts, don't forget to edit the startup...c file!
 */
void EusciA0_ISR(void)
{
    int receiveByte = UCA0RXBUF;
    MAP_GPIO_setOutputHighOnPin(GPIO_PORT_P1, GPIO_PIN0);
    /* Echo back. */
    MAP_UART_transmitData(EUSCI_A0_BASE, receiveByte);
    MAP_GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_PIN0);
}
int main(void)
{
volatile int i, j, temp;
volatile uint16_t test[NUM_ADC14_CHANNELS];
    /* Halting WDT  */
    MAP_WDT_A_holdTimer();
    initializeBackChannelUART();
Interrupt_enableMaster();
    while(!initializeADC())
    {
for(i=0;i<100;i++); // Wait to try again.
}
    /* Main while loop */
while(1)
{
/* Pulse the start of a conversion. */
printf("test\n");
while(!MAP_ADC14_toggleConversionTrigger()){
for(i=0;i<100;i++);  // Wait for conversion to finish.
}
for(i=0; i<NUM_ADC14_CHANNELS; i++){
test[i] = resultsBuffer[i];
}
}
}
int initializeADC(void){
    /* Initializing ADC (MCLK/1/1) */
    ADC14_enableModule();
    ADC14_initModule(ADC_CLOCKSOURCE_MCLK, ADC_PREDIVIDER_1, ADC_DIVIDER_1,
            ADC_NOROUTE);
    /* Configuring GPIOs for Analog In
     * Pin 4.1 is S21_Q, A12
     * Pin 4.3 is S21_I, A10
     * Pin 5.0 is S21_I, A5
     * Pin 5.1 is S21_Q, A3  */
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P5,
             GPIO_PIN1| GPIO_PIN0, GPIO_TERTIARY_MODULE_FUNCTION);
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P4,
            GPIO_PIN1 | GPIO_PIN3, GPIO_TERTIARY_MODULE_FUNCTION);
    /* Configuring ADC Memory (ADC_MEM0 - ADC_MEM3, with A12, A10, A5, A3
     * with no repeat) with VCC and VSS reference */
    if(!ADC14_configureMultiSequenceMode(ADC_MEM0, ADC_MEM3, false))
    return(0);
    if(!ADC14_configureConversionMemory(ADC_MEM0|ADC_MEM1|ADC_MEM2|ADC_MEM3,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A12, ADC_NONDIFFERENTIAL_INPUTS))
    return(0);
/*    if(!MAP_ADC14_configureConversionMemory(ADC_MEM1,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A10, ADC_NONDIFFERENTIAL_INPUTS))
    return(0);
    if(!MAP_ADC14_configureConversionMemory(ADC_MEM2,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A5, ADC_NONDIFFERENTIAL_INPUTS))
    return(0);
    if(!MAP_ADC14_configureConversionMemory(ADC_MEM3,
            ADC_VREFPOS_AVCC_VREFNEG_VSS,
            ADC_INPUT_A3, ADC_NONDIFFERENTIAL_INPUTS))
    return(0);*/
    /* Enabling the interrupt when a conversion on channel 3 (end of sequence)
     *  is complete and enabling conversions */
    ADC14_enableInterrupt(ADC_INT3|ADC_IN_INT);
    /* Enabling Interrupts */
    Interrupt_enableInterrupt(INT_ADC14);
    /* Setting up the sample timer to automatically step through the sequence
     * convert.
     */
    if(!MAP_ADC14_enableSampleTimer(ADC_AUTOMATIC_ITERATION))
    return 0;
    /* Enable conversion */
    if(!MAP_ADC14_enableConversion())
    return 0;
    return 1;
}
void initializeClocks(void)
{
    /* Initialize main clock to 48MHz.  To make it 3 MHz change the 48 to 3
     * and the 16's to 1.*/
    CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48); // Full speed
    CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_16 );
    MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_16 );
    MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_16 );
}
int initializeBackChannelUART(void){
initializeClocks();
    /* Selecting P1.2 and P1.3 in UART mode. */
    MAP_GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1,
        GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION);
    /* Configuring UART Module */
    if(MAP_UART_initModule(EUSCI_A0_BASE, &uartConfig)==STATUS_FAIL)
    return (STATUS_FAIL);
    /* Enable UART module */
    MAP_UART_enableModule(EUSCI_A0_BASE);
    /* Enable UART interrupts for backchannel UART */
    UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT);
    Interrupt_enableInterrupt(INT_EUSCIA0);
    return 1;
}
/*
 * printfOverride.c
 *
 *  Created on: May 27, 2015
 *      Author: Gerard Sequeira, 43oh
 *
 *  With input from:
 *       Printf_support_for_MSP430_CCSTUDIO_compiler
 */
/* DriverLib Includes */
#include "driverlib.h"
/* Standard Includes */
#include <stdio.h>
#include <string.h>
int fputc(int _c, register FILE *_fp);
int fputs(const char *_ptr, register FILE *_fp);
int fputc(int _c, register FILE *_fp)
{
  while(!(UCA0IFG&UCTXIFG));
  UCA0TXBUF = (unsigned char) _c;
  return((unsigned char)_c);
}
int fputs(const char *_ptr, register FILE *_fp)
{
  unsigned int i, len;
  len = strlen(_ptr);
  for(i=0 ; i<len ; i++)
  {
    while(!(UCA0IFG&UCTXIFG));
    UCA0TXBUF = (unsigned char) _ptr[i];
  }
  return len;
}

//*****************************************************************************
//
// Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// MSP432 Family Interrupt Vector Table for CGT
//
//****************************************************************************

#include <stdint.h>

/* Forward declaration of the default fault handlers. */
static void resetISR(void);
static void nmiISR(void);
static void faultISR(void);
static void defaultISR(void);


/* External declaration for the reset handler that is to be called when the */
/* processor is started */
extern void _c_int00(void);

/* External declaration for system initialization function */
extern void SystemInit(void);

/* Linker variable that marks the top of the stack. */
extern unsigned long __STACK_END;


/* External declarations for the interrupt handlers used by the application. */
extern void ADC14_IRQHandler(void);
extern void EusciA0_ISR(void);
/* To be added by user */


/* Interrupt vector table. Note that the proper constructs must be placed on this to */
/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
/* the program if located at a start address other than 0. */
#pragma RETAIN(interruptVectors)
#pragma DATA_SECTION(interruptVectors, ".intvecs")
void (* const interruptVectors[])(void) =
{
(void (*)(void))((uint32_t)&__STACK_END),
/* The initial stack pointer */
resetISR, /* The reset handler */
nmiISR, /* The NMI handler */
faultISR, /* The hard fault handler */
defaultISR, /* The MPU fault handler */
defaultISR, /* The bus fault handler */
defaultISR, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
defaultISR, /* SVCall handler */
defaultISR, /* Debug monitor handler */
0, /* Reserved */
defaultISR, /* The PendSV handler */
defaultISR, /* The SysTick handler */
defaultISR, /* PSS ISR */
defaultISR, /* CS ISR */
defaultISR, /* PCM ISR */
defaultISR, /* WDT ISR */
defaultISR, /* FPU ISR */
defaultISR, /* FLCTL ISR */
defaultISR, /* COMP0 ISR */
defaultISR, /* COMP1 ISR */
defaultISR, /* TA0_0 ISR */
defaultISR, /* TA0_N ISR */
defaultISR, /* TA1_0 ISR */
defaultISR, /* TA1_N ISR */
defaultISR, /* TA2_0 ISR */
defaultISR, /* TA2_N ISR */
defaultISR, /* TA3_0 ISR */
defaultISR, /* TA3_N ISR */
EusciA0_ISR, /* EUSCIA0 ISR */
defaultISR, /* EUSCIA1 ISR */
defaultISR, /* EUSCIA2 ISR */
defaultISR, /* EUSCIA3 ISR */
defaultISR, /* EUSCIB0 ISR */
defaultISR, /* EUSCIB1 ISR */
defaultISR, /* EUSCIB2 ISR */
defaultISR, /* EUSCIB3 ISR */
ADC14_IRQHandler, /* ADC14 ISR */
defaultISR, /* T32_INT1 ISR */
defaultISR, /* T32_INT2 ISR */
defaultISR, /* T32_INTC ISR */
defaultISR, /* AES ISR */
defaultISR, /* RTC ISR */
defaultISR, /* DMA_ERR ISR */
defaultISR, /* DMA_INT3 ISR */
defaultISR, /* DMA_INT2 ISR */
defaultISR, /* DMA_INT1 ISR */
defaultISR, /* DMA_INT0 ISR */
defaultISR, /* PORT1 ISR */
defaultISR, /* PORT2 ISR */
defaultISR, /* PORT3 ISR */
defaultISR, /* PORT4 ISR */
defaultISR, /* PORT5 ISR */
defaultISR, /* PORT6 ISR */
defaultISR, /* Reserved 41 */
defaultISR, /* Reserved 42 */
defaultISR, /* Reserved 43 */
defaultISR, /* Reserved 44 */
defaultISR, /* Reserved 45 */
defaultISR, /* Reserved 46 */
defaultISR, /* Reserved 47 */
defaultISR, /* Reserved 48 */
defaultISR, /* Reserved 49 */
defaultISR, /* Reserved 50 */
defaultISR, /* Reserved 51 */
defaultISR, /* Reserved 52 */
defaultISR, /* Reserved 53 */
defaultISR, /* Reserved 54 */
defaultISR, /* Reserved 55 */
defaultISR, /* Reserved 56 */
defaultISR, /* Reserved 57 */
defaultISR, /* Reserved 58 */
defaultISR, /* Reserved 59 */
defaultISR, /* Reserved 60 */
defaultISR, /* Reserved 61 */
defaultISR, /* Reserved 62 */
defaultISR /* Reserved 63 */
};


/* This is the code that gets called when the processor first starts execution */
/* following a reset event. Only the absolutely necessary set is performed, */
/* after which the application supplied entry() routine is called. Any fancy */
/* actions (such as making decisions based on the reset cause register, and */
/* resetting the bits in that register) are left solely in the hands of the */
/* application. */
void resetISR(void)
{
SystemInit();

/* Jump to the CCS C Initialization Routine. */
__asm(" .global _c_int00\n"
" b.w _c_int00");
}

/* This is the code that gets called when the processor receives a NMI. This */
/* simply enters an infinite loop, preserving the system state for examination */
/* by a debugger. */
static void nmiISR(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")

/* Enter an infinite loop. */
while(1)
{
}

#pragma diag_pop
}


/* This is the code that gets called when the processor receives a fault */
/* interrupt. This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger. */
static void faultISR(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")

/* Enter an infinite loop. */
while(1)
{
}

#pragma diag_pop
}


/* This is the code that gets called when the processor receives an unexpected */
/* interrupt. This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger. */
static void defaultISR(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")

/* Enter an infinite loop. */
while(1)
{
}

#pragma diag_pop
}

  • 0
    Guru 11940 points

    Perhaps something simple like a stack overflow. However, the posted code is hard to read, since not formatted as code, but as simple text.

    I suggest to start with working backwards - when the hardfault occured, read out the status registers in the system control block. They tell you about the reason.

    Here is a good document, describing how to do it: keil.com/appnotes/files/apnt209.pdf

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