MSP430F2618 SPI slave not syncing with master clock

Hi, I'm trying to have two duplicate MCUs communicate via SPI, with one as a master and the other as a slave. The master pulls the chip select line low, and then starts sending bytes (counts up to 127) on MOSI with 50 us intervals between bytes. Meanwhile, the Slave (shown below) waits for CS to go low before enabling SPI, at which point it starts sending bytes on MISO (it also counts up to 127 with 50 us intervals between bytes), but while the bytes coming from the master are correct, the bytes being sent by the slave seem to skip bytes in the sequence. Sometimes the intervals between bytes are regular, e.g., it sends 0x02, 0x04, 0x06, etc., but sometimes there doesn't seem to be any logical progression. The code below is for the slave, but I can also include the code for the master if that would be helpful. I've tried both with and without a 50 us delay between bytes on the slave side, but neither one works

First, could someone tell me if I'm implementing this correctly? Should CS enable SPI, or should I use some other method to sync master and slave? Should I include the delay between bytes on the slave side, or should I rely on the absence of a clock signal to dictate the delays between bytes? Perhaps using an edge trigger for the CS line would be better? Any help would be greatly appreciated. Thank you

#include "io430.h"

void initialize_pins();
void initialize_clocks();
void initialize_SPI();
unsigned char write_byte0(unsigned char byte);

int j = 0;
unsigned char RX[4] = {0x00}, AFC_data[128] = {0x00};

void main( void )
{
WDTCTL = WDTPW + WDTHOLD;
__bis_SR_register(GIE); // General interrupt enable

initialize_pins();
initialize_clocks();
initialize_SPI();

while(1)
{
if (P2IN & 0x02) // Wait for Chip select line to go low
{
UCB0CTL1 |= UCSWRST;
}
else
{
UCB0CTL1 &= ~UCSWRST; // Enable SPI
//__delay_cycles (50);
write_byte0(j);
j++;
if (j == 127)
j = 0;
}
}
}

void initialize_clocks()
{
// Turning on XTAL2
BCSCTL3 |= XT2S1; // Allow external 3-16 MHz crystal
BCSCTL1 &= ~XT2OFF; // Turn on XT2

// Displaying SMCLK (from XTAL2) on P1.4:
BCSCTL2 |= SELS; // Source SMCLK from XT2
BCSCTL2 |= DIVS1; // Divide SMCLK by 4 = 4MHz
}

void initialize_SPI()
{
UCB0CTL1 |= UCSWRST; // Hold MCU in reset state during config
UCB0CTL0 |= UCCKPH; // Rising edge
UCB0CTL0 |= UCMSB; // MSB first
UCB0CTL0 &= ~UCMST; // Slave
UCB0CTL0 |= UCSYNC; // Synchronous
P3SEL |= 0x0E; // P3.1,2,3 Select MOSI, MISO, SCLK
UCB0CTL1 &= ~UCSWRST; // Release MCU reset state

}

unsigned char write_byte0(unsigned char byte) // B0: SPI to EBM
{
while (IFG2 & UCB0TXIFG == 0); // Wait for TX buffer to clear
UCB0TXBUF = byte; // Send byte of CMD0
while (IFG2 & UCB0RXIFG == 0); // No hanging w/SPI b/c MCU waits for 8 clock pulses, not data
return (UCB0RXBUF); // Read in MISO data
}