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MSP430F6659 DCO ISSUE

Krishn_JI
Expert 2145 points

Other Parts Discussed in Thread: MSP430F6659

i am working on MSP430F6659

here in ucs system my code is 

int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

UCSCTL0_H |= 0b00011111;
UCSCTL0_L &= 0b00000000;
UCSCTL1 |= DCORSEL_7;
UCSCTL4 |= SELS_4;

__delay_cycles(100000);

P3DIR |= BIT4;
P3SEL |= BIT4;

}

my question is how to get maximum clk frequency = 135mhz.

when i am compiling above code on ccs6 it shows all DCO bits are 0 and all the MOD bits are 1. What should i do?

  • 0
    Guru 325150 points

    These bits are automatically changed by the FLL. You need to disable the FLL (set SCG0).

    And there is no guarantee that you will reach 135 MHz; the datasheet guarantees only that these settings will result in some random frequency between 60 MHz and 135 MHz.

    And overclocking beyond 20 MHz is not guaranteed to succeed, unless "success" includes a melted CPU.

    And before going beyond 8 MHz, you must increase PMMCOREV (see section 2.2.4 of the User's Guide).

  • 0 in reply to Clemens Ladisch
    Expert 2145 points
    Hi Clemens Ladisch

    Thank you for you reply . . .

    I have tried as per your suggestion but there is no effect....
  • 0 in reply to Krishn_JI
    Guru 34973 points

    It is better to use XT2 for overclocking than DCO.

    I have few boards that are working on doubled MCLK (40 / 48 MHz) specified in datasheet (20 / 24 MHz) on 3.3 V.

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