I am having trouble understanding the code of Code Composer Studio .
Especially italics part. It would be very helpful if you explain the whole code.
For e,g,
#include "msp.h"
#include "stdint.h"
void error(void);
int main(void)
{
uint32_t currentPowerState;
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
/* NOTE: This example assumes the default power state is AM0_LDO.
* Refer to MSP4322001_pcm_0x code examples for more complete PCM operations
* to exercise various power state transitions between active modes.
*/
/* Step 1: Transition to VCORE Level 1: AM0_LDO --> AM1_LDO */
/* Get current power state, if it's not AM0_LDO, error out */
currentPowerState = PCM->CTL0 & PCM_CTL0_CPM_MASK;
if (currentPowerState != PCM_CTL0_CPM_0)
error();
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
if (PCM->IFG & PCM_IFG_AM_INVALID_TR_IFG)
error(); // Error if transition was not successful
if ((PCM->CTL0 & PCM_CTL0_CPM_MASK) != PCM_CTL0_CPM_1)
error(); // Error if device is not in AM1_LDO mode
/* Step 2: Configure Flash wait-state to 2 for both banks 0 & 1 */
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & (~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_2;
FLCTL->BANK1_RDCTL = FLCTL->BANK0_RDCTL & (~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_2;
/* Step 3: Configure DCO to 48MHz, ensure MCLK uses DCO as source*/
CS->KEY = CS_KEY_VAL ; // Unlock CS module for register access
CS->CTL0 = 0; // Reset tuning parameters
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
/* Select MCLK = DCO, no divider */
CS->CTL1 = CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM_3;
CS->KEY = 0; // Lock CS module from unintended accesses
/* Step 4: Output MCLK to port pin to demonstrate 48MHz operation */
P4DIR |= BIT3;
P4SEL0 |=BIT3; // Output MCLK
P4SEL1 &= ~(BIT3);
/* Go to sleep */
__sleep();
__no_operation(); // For debugger
}
void error(void)
{
volatile uint32_t i;
P1DIR |= BIT0;
while (1)
{
P1OUT ^= BIT0;
for(i=0;i<20000;i++); // Blink LED forever
}
}
