msp430fr5969 i2c problem

Hello folks,

I want to ask two question about i2c interface. I am trying to communicate with a sensor via i2c and i generated read and write functions. The functions are working seperately very well. But when  I try to call the write function just after the read function the bus hangs. Also When I call two consecutive read functions the problem occurs again. But  when I call two consecutive write function there is no problem. My code and scope outputs are below.

The second question is that,  I try to read only one byte but the msp reads two byte consecutively. I see 16 clock cycles for data read. Any idea why those situations happens?

The code hangs on  this line "__bis_SR_register(CPUOFF + GIE); " 

and there is no transmit interrupt comes to get the cpu out of lpm0 state 

Thank you for your helps

#pragma vector = USCI_B0_VECTOR
__interrupt void USCIB0_ISR(void)
{

  static uint8_t count = 0;
  switch(__even_in_range(UCB0IV,0x1a))
  {
    case 0x00: break;                           // Vector 0: No interrupts break;
    case 0x02: break;
    case 0x04:

    	EUSCI_B_I2C_masterSendStart(EUSCI_B0_BASE);

    	break;
    case 0x16:

      *RXData++ = EUSCI_B_I2C_masterReceiveSingle(EUSCI_B0_BASE);                           // Get RX data

      if(++count >= RXByteCtr)
      {
    	  EUSCI_B_I2C_masterReceiveMultiByteStop(EUSCI_B0_BASE);
    	  count = 0;
          EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_RECEIVE_INTERRUPT0);

          __bic_SR_register_on_exit(CPUOFF);               // Exit LPM0
      }

      break;
    case 0x18:
    	if(TXByteCtr)                         // Check TX byte counter
		{
			EUSCI_B_I2C_masterSendMultiByteNext(EUSCI_B0_BASE,*TXData++);
			TXByteCtr--;                        // Decrement TX byte counter
		}
		else
		{
			if(Read==0)
			{
				EUSCI_B_I2C_masterSendMultiByteStop(EUSCI_B0_BASE);
			}
			EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0);
			__bic_SR_register_on_exit(CPUOFF);    // Exit LPM0
		}

      break;                                    // Vector 26: TXIFG0 break;
    case 0x1a:
      HWREG16(EUSCI_B0_BASE + OFS_UCBxIFG) &= ~UCBCNTIFG;
      break;
    default: break;
  }
}

void i2c_write( unsigned char* ic2txPtr, uint16_t len)
{
  Read =0;
  TXData= ic2txPtr;
  TXByteCtr = len;                      // Load TX byte counter

  //Specify slave address
  EUSCI_B_I2C_setSlaveAddress(EUSCI_B0_BASE,SLAVE_ADDRESS_2);
  EUSCI_B_I2C_setMode(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_MODE);
  EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0 +EUSCI_B_I2C_NAK_INTERRUPT);
  EUSCI_B_I2C_enableInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_NAK_INTERRUPT);


  while(EUSCI_B_I2C_SENDING_STOP == EUSCI_B_I2C_masterIsStopSent
            (EUSCI_B0_BASE))
  {
      ;
  }

  EUSCI_B_I2C_masterSendMultiByteStart(EUSCI_B0_BASE, *TXData++);

  __bis_SR_register(CPUOFF + GIE);        // Enter LPM0 w/ interrupts

}

void i2c_read(unsigned char* ic2rxPtr, uint16_t len)
{

  Read =1;
  TXData= ic2rxPtr;
  TXByteCtr = 0;

  //Specify slave address
  EUSCI_B_I2C_setSlaveAddress(EUSCI_B0_BASE,SLAVE_ADDRESS_2);
  //Set Master in receive mode
  EUSCI_B_I2C_setMode(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_MODE);

  EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_NAK_INTERRUPT);

  //Enable master Receive interrupt
  EUSCI_B_I2C_enableInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_NAK_INTERRUPT);


  while(EUSCI_B_I2C_SENDING_STOP == EUSCI_B_I2C_masterIsStopSent
			(EUSCI_B0_BASE))
  {
	  ;
  }


  EUSCI_B_I2C_masterSendMultiByteStart(EUSCI_B0_BASE, *TXData++);

  __bis_SR_register(CPUOFF + GIE);        // Enter LPM0 w/ interrupts
  __no_operation();                       // Remain in LPM0 until all data



  RXByteCtr = len;

  //Specify slave address
  EUSCI_B_I2C_setSlaveAddress(EUSCI_B0_BASE, SLAVE_ADDRESS_2);

  //Set Master in receive mode
  EUSCI_B_I2C_setMode(EUSCI_B0_BASE,EUSCI_B_I2C_RECEIVE_MODE);

  EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_RECEIVE_INTERRUPT0 + EUSCI_B_I2C_NAK_INTERRUPT);

  //Enable master Receive interrupt
  EUSCI_B_I2C_enableInterrupt(EUSCI_B0_BASE,EUSCI_B_I2C_RECEIVE_INTERRUPT0 + EUSCI_B_I2C_NAK_INTERRUPT);

  //Set Master in receive mode
  EUSCI_B_I2C_setMode(EUSCI_B0_BASE,EUSCI_B_I2C_RECEIVE_MODE);

  while(EUSCI_B_I2C_SENDING_STOP ==
        EUSCI_B_I2C_masterIsStopSent(EUSCI_B0_BASE))
  {
      ;
  }

  EUSCI_B_I2C_masterReceiveStart(EUSCI_B0_BASE);


  __bis_SR_register(CPUOFF + GIE);     // Enter LPM0 w/ interrupts
  __no_operation();                       // Remain in LPM0 until all data

}