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(MSP430F5659) ADC12, REF and Accuracy

k1mgy
Expert 1680 points

Other Parts Discussed in Thread: MSP430F5659


On page 77 of the MSP430F5659 data sheet, below the table "REF, External Reference", are several footnotes.  These seem to suggest that when one uses any external reference below aVcc, accuracy is reduced.  "Lower reference voltage levels may be applied with reduced accuracy requirements."

This statement is puzzling. 

First, I might assume that a 2,5V reference on VeREF+ (with VeREF- at AGND) will yield 12 bits across 0 to 2.5V (610 microvolts/bit).  Whereas, a 3.3V VeREF+ (or using AVCC set at 3.3V) will yield 850 microvolts/bit. 

So, is TI telling us that even if we use a VeREF+ that's lower than aVCC, and can therefore resolve the input to greater resolution, our "accuracy" will be only as good as the full span of aVcc?

Also, puzzlement as to the use of VeREF-.  Is this to allow inputs slightly below aGND?  I thought these were illegal and would violate pin voltage limits.  What other purpose might VeREF- serve?

  • 0
    Guru 325160 points
    Reducing the differential external reference voltage will make the voltage for each ADC step smaller, i.e., increase the precision, but I'd guess that due to noise, the results will not be more accurate.

    The datasheet shows that VeREF− must not be below 0 V; the footnote for that entry says "higher".
  • 0 in reply to Clemens Ladisch
    TI__Intellectual 1330 points
    About the external reference voltage, the datasheet says, that reference voltage should be in range of 1.4 volts to AVcc. The footnote tells you that lower reference voltage levels (< 1.4 volts ) may be applied with reduced accuracy requirements.

    The use of the VeRef- input was already explained by Clemens. You can use it for higher voltages than GND and not for lower voltages.

    Best regards,
    Tobias
  • 0 in reply to Clemens Ladisch
    Expert 1680 points
    It would be good to have the inaccuracy quantified. TI have anything to add here?
  • 0 in reply to Tobias Oschmann
    Expert 1680 points
    So, from this I take it that one can use both VeREF- and VeREF+ to set an ADC sampling window, with VeREF- > 0 (ideally > 1.4V) and VeREF+ < AvCC?
  • 0 in reply to k1mgy
    TI__Intellectual 1330 points
    Yes, you can use both to reduce the input voltage range for the ADC and to decrease the voltage per step. But your assumption about the applied voltages are not right. Page 77 on the datasheet says that:
    VeREF+ should be in range of 1.4 volts up to AVcc (or lower than 1.4 volts but with reduced performance)
    VeREF- should be in range of 0 volts up to 1.2 volts (or higher than 1.2 volts but with reduced performance)

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