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SPI transaction time

Prad
Expert 1125 points
Other Parts Discussed in Thread: MSP430F5529, MSP430F5438

Hi,

 

I am using SPI to communicate between MSP430F5529(Mst) and MSP430F5438(Slv),

and using RX interrupt it is taking around 4us to 5us to receive one byte of data at 5MHz clock.

Is there any way to speed up this SPI comm in MSP430?

And would like to know how much time does it take for the UCRXIFG flag to set after the SPI transaction gets started. 

 

Thankyou,

  • 0
    TI__Mastermind 26380 points

    Prad,

    If you are using the interrupt service routine with the RXIE enabled you should know that the latency of servicing the interrupt is 5MCLK cycles.

    If you are programming in C you may need to add the time taken to perform any context saves that are done on entry into the ISR.

    See the diassembly window to know exactly how many instructions are executed before getting to the RX read.

    Also; note that for a SPI master,  the max. SPI clock allowed is the system clock Fsystem i.e. MCLK needs to be atleast 5MHz to run a 5MHz SPI clock.

    The recommendation is that MCLK is run at higher speeds to reduce data handling overhead time.

    You can always use DMA to transfer the data from RXBUF to storage location. There is no latency with servcing the DMA  request and it will take 2 MCLK cycles to complete.

    Prad said:

    And would like to know how much time does it take for the UCRXIFG flag to set after the SPI transaction gets started. 

    Once the RX shift register has received a byte it takes 2 MCLK cycles to move it to RXBUF. As soon as the data is moved to RXBUF the RXIFG flag is set.  (see USCI SPI chapter in UG)

    Regards,

    Priya

     

  • 0
    Prodigy 30 points

    Prad said:
    receive one byte of data at 5MHz clock.

    Hi Prad,

    Do you think you can share your configuration setup as I have been trying to achieve an SPI clock rate around that value?  When I push above 900kHz, the data frame transmits twice.

    Thanks for you help,

    Zach

     

    [update]  I have since resolved the problem.  MCLK was defined to use the 35kHz crystal and should have been configured at 7.3 MHz crystal.

  • 0 in reply to Zach Jacobs
    Guru 227245 points

    I had no problems sending and receiving in master mode with 4MHz SPI clock (8MHz MCLK) on a 1611 to an SD card.

    On the 5438, I successfully transmitted blocks of data with 16MHz SPI clock and read them back (SOMI and SIMO connected) with DMA and manually feeding the buffers.

    In slave mode, the 5438 allows at most MCLK/2 for SPI. Better less. Remember that the clock settings do not apply at all in slave mode and the clock is dictated by the master. Which might be asynchroneous to MCLK. that's why there is half the MCLK as maximum.

    Also, you'll have only 16 clock cycles per byte for entering the RX  ISR, saving all used registers to stack, do the receive job, restore the registers, return, enter the TX ISR (if there is bidirectional transfer) etc. I'd say: no way!

    Go for DMA if you need such a high transfer rate. And define a really long delay between setting CS low in the communication protocol, so the slave MSP can set up things in time. Once the master sends the first clock, things have to be ready. The master won't wait.

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