MSP430F5338 setting

Thanks, Its all matching with my current setting. The issue I'm facing with this setting is that the UART output sometimes seen as junk. Is this setting affect the UART in anyway? I have following settings,

P7SEL |= BIT2; // set Port pins are used as clock source

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000;
UCSCTL1 = 0x0040; // DCORSEL set as 4 in bit 6- 4 for 20MHz
UCSCTL2 = 0x0001; // set FLL loop divider = f(DCOCLK)/1. In bit 14-12
// (000) Multiplier bits set as 1 in bits 9-0
__bic_SR_register(SCG0); // Enable the FLL control loop

UCSCTL5 |= 0x0000; // ACLK source divider = 0
// SMCLK source divider = 0
// MCLK source divider = 0
UCSCTL6 &= ~(0x0100); // Enable XT2
UCSCTL3 |= 0x0050; // select FLL ref source as XT2CLK
UCSCTL4 |= 0x0500; // select ACLK source as XT2CLK

do
{
UCSCTL7 &= ~(0x000B); // checking OSC fault flags
SFRIFG1 &= ~(0x0002);
} while (SFRIFG1&0x0002);

// XT2DRIVE0 set as 10 in bit 15-14 to select freq range is 16 - 24 MHz
// Turn ON XT2 by set bit 8 as 0
UCSCTL6 &= ~(0x4000);
UCSCTL6 |= 0x1000; // XT2 sourced from External OSC
UCSCTL4 |= 0x055; // select SMCLK, MCLK sourcs as XT2CLK
UCSCTL7 |= 0x0000; // No osc Fault occured after last reset
UCSCTL8 |= 0x0707;