MSP430F5529 to Maxim 31865

That interface is called SPI.

The only interesting wrinkle is that the MAX31865 makes its output high impedance when not sending anything, so you should enable the pull-up or -down resistor on the SOMI pin. But other than that, look at the SPI examples.

For chip select, how would I configure the MSP 430 to have a CS signal going to each of five identical MAX31865 slaves?

Just use a bunch of GPIO pins.

Got it, thanks a ton. I have one more basic question, is SDO or DRDY the SOMI pin on the MAX31865?

SDO is SOMI.

The datasheet says:

D̅R̅D̅Y̅ goes low when a new conversion result is available in the data register. When a read operation of an RTD resistance data register occurs, D̅R̅D̅Y̅ returns high.

So that pin is supposed to be connected to a GPIO input with an interrupt on the master.

OK, thanks. That makes sense.

However, I only have (6) available GPIO pins on the MSP430, so with individual CS and DRDY signals from (5) Maxim 31865 chips, how would I make that configuration work? If it means anything, I am only doing read operations from the MSP430 to the Maxim 31865 chips.

Do you actually need the DRDY signals? Do you need to differentiate them, or could you combine them with an AND logic gate?