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NMI showing up in reset vector?

Other Parts Discussed in Thread: MSP430F5659

Processor: MSP430F5659

I have a situation where the signals feeding *RST may be unreliable (don't ask).  I am playing with switching the *RST function to the NMI functionality.  I am most of the way there.  However, often while generating the NMI, i end up with a reset and the SYSRSTIV being 0x04 = *RST/NMI.    If SFRRPCR is left with a setup of SYSNMI|SYSNMIIES|SYSRSTUP|SYSRSTRE, how can this happen ?

  • Hi Jim,

    normally no RST should be triggered once you configured the RST/NMI pin as NMI as you described above. Following thing to check.

    1. Is the NMI interrupt vector and the corresponding ISR defined and handled correclty

    2. Are you sure that the unreliable RST signal is reliable until you define the RST pin to  NMI because if somehting on RST pin happens before a reset is triggered.

    Best regards,
    Dietmar

  • 1) Yes; NMI triggers correctly, as evidence by toggling an external debug pin tied to a scope

    2) Yes; this is happening in 'steady state' condition, with reliable *RST on my desk (i'm dealing with a field condition).  i'm also polling SFRRPCR to see if it changes from the 0xF setting.

  • i have altered my code to simply count the nmi's, and check the count out in the main loop, and trigger a software POR at that point. I save the PMMIFG register coming out of reset.

    What I get (rs is saved SYSRSTIV; pmm is saved PMMIFG):

    if ( nmiCount >= 0x0F ) // counting is fine, but still getting RST vector when it is done!
    {
    printf ( "too many nmi\r\n" );
    ConsoleFlush ( );
    PMMCTL0_H = 0xA5; // Unlock it
    PMMCTL0_L |= PMMSWPOR;
    PMMCTL0_H = 0x00;
    }

    too many nmi
    save_ifg1: x6 rs: 14 Vcap 4829 = lastR x14 nmi 20 pmm 400 << expected
    ===
    too many nmi
    save_ifg1: xE rs: 4 Vcap 4866 = lastR x4 nmi 17 pmm 600 << vector 4 unexpected with PMMPORIFG already set
  • Hi Jim,

    sorry but I could not 100% follow you last post. So does it mean when you counted 16 NMI that then a the 0x04 (RST pin event) appear if the SYSRSTIV?

    Did you ensured that during your intial start-up you read the SYSRSTIV until it is ZERO using something like this below:

    //******************************************************************************

    //   Functionname: Init_SYSRSTIV

    //   Description:  Evaluate the reset vector after a restart.

    //

    //******************************************************************************

    void Init_SYSRSTIV(void)

    {

     unsigned int tmp;

     while(1){

       switch (__even_in_range(SYSRSTIV, 0x3E))

       {

         case 0x00:  return;                      //No more Flags      

         case 0x02:{tmp=BOR_Flag;         break;}//BOR

         case 0x04:{tmp=RSTNMI_Flag;      break;}//RSTNMI

         case 0x06:{tmp=OtherRst_Flag;    break;}//PMMSWBOR

         case 0x08:{tmp=OtherRst_Flag;    break;}//LPMx.5 WkUp

         case 0x0A:{tmp=Violation_Flag;   break;}//Security Violation

         case 0x0C:{tmp=SVSL_Flag;        break;}//SVSL BOR

         case 0x0E:{tmp=SVSH_Flag;        break;}//SVSH BOR

         case 0x14:{tmp=OtherRst_Flag;    break;}//SW POR

         case 0x16:{tmp=WDT_Flag;         break;}//WD timeout PUC

         case 0x18:{tmp=Violation_Flag;   break;}//WD PW violation

         case 0x1A:{tmp=Violation_Flag;   break;}//Flash password violation(PUC)

         case 0x1C:{tmp=OtherRst_Flag;    break;}//Reserved

         case 0x1E:{tmp=OtherRst_Flag;    break;}//area fetch

         case 0x20:{tmp=Violation_Flag;   break;}//PMM PW violation

         case 0x22:{tmp=OtherRst_Flag;   break;}//Reserved

         case 0x24:{tmp=OtherRst_Flag;   break;}//Reserved

         case 0x26:{tmp=OtherRst_Flag;   break;}//Reserved

         case 0x28:{tmp=OtherRst_Flag;   break;}//Reserved

         case 0x2A:{tmp=OtherRst_Flag;   break;}//Reserved

         case 0x2C:{tmp=OtherRst_Flag;   break;}//Reserved

         default:  {tmp=OtherRst_Flag;    break;}  

       }

       Set_FaultFlag(tmp);

     }

    }

    Does this problem appear only on single units or is this a general problem?

    Do you struggle with EM noise in the application environment?

    Best regards,

    Dietmar

  • No I don't have a loop like that, but i'll take that under consideration.  The example in the user guide does not loop, but the explanatory paragraph does imply it.

    Upon further reflection of my test setup on my desk and your example, I suspect that the RST reset is occurring after my intentional one (since it is just noisy and I have no control), and that is what I end up seeing - which is why there were 2 flags indicated in the PMMIFG.  Once I removed my intentional reset, NMI behaved as expected.

    We are struggling with EM noise on this pin; caps have been added to RST/NMI and to SBWTCK, although the values may be higher than desired.

  • Hi Jim,
    sounds like you have it now correct?

    So if you struggle with EM noise I recommend to redcue the loop inductance of the RSTNMI singal to reduce the impact of inductive coupling to the this signal. Means placing the cap and the pull up very close to the pin with very good GND/DVCC connection.
    Also something like a 10 Ohm serial resistance might help but depends on application if possible.

    I also recommend to read the MSP430 System Level ESD considerations which gives you general guidelines which needs to be considered for a more robust application design.
    www.ti.com/lit/pdf/slaa530

    Best regards,
    Dietmar
  • well, that side is ok, sort of. Directly related though....

    The resets are apparently coming via the SBWTCK line. I found several references on this support board to problems with that line. We tested by repeatedly pulling that line high; with non-NMI code, processor would reset & indicate RST vector (so a bit of a red herring on that)

    Oddly enough - at least to me - is that switching RST to NMI, and then doing that same test, I was able to mask the reset generated via our SBWTCK test; my count logic verified that the NMI was being used in this case.

    I found no documentation regarding SBWTCK & RST/NMI ???
  • Jim,

    to understand you right you already know that noise couples via SBWTCK pin and triggers the RESET or the NMI (depending on RST/NMI pin configuration).
    Does this also meant that if you lift up the SBWTCK lead of the device the issue disappears?

    Best regards,
    Dietmar
  • Existing circuit on SBWTCK is 100ohm series, followed by pull-down of 4.75K. By touching this pin on our jtag port to Vcc (multiple times), the reset is triggered.
  • Do you have scope shots of the RST and TEST pin while you do this touch experiements would be interesting if any fast spikes might appear on these lines.

  • Unfortunately, due to the high-energy issues of this setup, especially using a Hi-Pot tester, we can't get scope traces.  10nF has been added to RESET (we have an open question regarding that to another TI person), and no resets are seen there, but i'll see if in the by-hand scenario we can generate something.

    When done by hand (simply pulling SBWTCK high by touching a test point), the reset occurs, so there should be no spikes occurring in that scenario.

  • Pulling TEST pin high would be you enable the JTAG interface. Is anything connected to the PortJ pins which migh be influenced by this?
  • no, JTAG pins are not used for anything else.

    We did 3 more tests with a scope, and NOT high energy. Scope probe on RST pin.
    1) Touching the SBWTCK to Vcc (noisy impulse). This induced noise on the RST line, and caused resets.
    2) Function generator to create a clean pulse on SBWTCK, low hertz single shots. No noise on RST, no resets.
    3) Function generator with clean pulses, 12KHz & higher. Observed SBWTCK going low, with RST pulled low at same time for ~40usec. When SBWTCK line goes high, RST does an RC rise to normal level over 120usec, but NO resets ?!? Picture available, but I don't know how to send.

    So, it seems to us that somehow the RST line is coupled into the SBWTCK line internally to the processor.
  • Jim,

    in your test #1 you apply a positive pulse on SBWTCK which couples to RST line

    However in test #2 and #3 you apply negative ones? Which amplitude the pulses have?

    To attach pictures you have to use rich formatting (right corner of the posting window) and then you can post pictures or attach files.
    Would be interested in the scope shots to get a better understanding.

    Best regards,

    Dietmar

  • The positive pulse 'by hand' generated some kind of noise coupled back onto the RST line.  When a positive controlled pulse was applied, that did not occur.  We also applied a higher-than-normal pulse on the SBWTCK to simulate the higher energy level (though we kept it 'reasonable').   Green is SBWTCK; Blue is RST, scope probe only on that signal.

    Picture attached.

  • Thanks for the valuable scope shot! Looks like you apply 5V pules on TEST pin which far beyond specification but I assume you know this.
    However really looks strange that the RST pin follows the TEST pin at a specific rising edge.

    One question how step is the falling edge? Could it be that due to PCB layout a a large overswing is received on the device TEST pin so that the ESD diodes might get triggered?

    The other problem I see is that you might pump energy into the system via the ESD diodes. See more on this in the following Apps Note
    www.ti.com/lit/an/slaa689/slaa689.pdf

    Sorry to answer all these questions but I have never seen something link this before:
    1. To ensure that the coupling does not appear on PCB level can you please disconnect the RST pin from PCB and check the pin with probe connected to the lead only?
    2. Would this problem also appear if you apply 3V or 3.6V pulses to operate in the allowed supply range?

    Best regards,
    Dietmar
  • We'll try SBWTCK in the lower range; we exceeded by a small amount to simulate the high-energy that we think is being imposed. For the rest... that will take some time, but we'll see what we can do, thanks.
  • Hi Jim,

    any update on this thread? Were you able to get rid of the unexpected resets?
  • Via separate hardware contact @ Ti, we ended up with 5.6nF cap on the SBWTCK line; 10nF was too much for the TI FET pod & debugger to function.  Also added code for the RST line to change to NMI & ignore the reset.  That code is necessary for deployed units that can't be recalled.  The loop to acquire the reset vector was an interesting twist to the entire problem as well.

  • Hi Jim,

    thanks for information so I will close this thread and we can mark it as answered.

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