Other Parts Discussed in Thread: CC430F6137
Has anyone managed to get MCLK to map to an output pin on a CC430F6137? I am able to get ACLK out on pins P2.4 or P2.6, but when I set those same pins to PM_MCLK (PM_MCLK == 4 in my book) all I get is 32768Hz (ACLK), no matter what I set MCLK to.
So, this example works as I expect (LCD and UART display/debug code removed for clarity):
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP4 = PM_ACLK; // map ACLK or MCLK to P2.4
P2MAP6 = PM_ACLK; // map ACLK or MCLK to P2.6
PMAPPWD = 0;
P2DIR |= (BIT4 | BIT6); // set xCLK signals out to pins
P2SEL |= (BIT4 | BIT6); // set mapped outputs for P2.4, P2.6:
for (clk = 0; clk <=5; clk++)
{
UCSCTL4 = (clk<<8) + (4<<4)+ (4<<0);
delay(50);
for (X=0; X<5; X++)
{
delay(250);
}
}
And I can measure the correct output pin values (32768, ~10kHz, ~33kHz, 2.1MHz, 1.048MHz respectively).
Then I change "PM_ACLK" to "PM_MCLK" and repeat with the loop from clk=3 to clk=5 and I use
UCSCTL4 = (0<<8) + (4<<4)+ (clk<<0);
The output pins show only 32768Hz.
I've tried this with both XX430 and CC430 (rev D) chips.
SMCLK is driving the UART based on a 1.048MHz DCO clock, and I print status throughout the above test code (printing removed for clarity) using the UART. So I'm pretty sure the DCO is really 2MHz, DCODIV is really 1MHz, SMCLK is 1.048Mhz, and ACLK is really 32768Hz. I even think that MCLK is 1.048MHz. I just can't output it onto a pin to prove it.
Any ideas?
Thanks,
Neal
