Multiple source flag

If an IRQ is accepted and the processor has fetched the proper interrupt vector, the procesor will report this to the hardware module that requested this interrupt. So thehardware knows that its request is being handled right now and can decide what to do:

Some interrupts have just one source. Such as the TACCR0 interrupt. Only TACCR0IFG will trigger it. So once the ISR is executed, the TACCR0IFG bit is cleared and you don't have to do anything about it.

Other interrupt sources share the same interrupt vector. Such as TAIFG, TACCR1 and TACCR2. Here, the IFG bit isn't cleared automatically when the ISR is entered. Either you check the proper register for all set bits and clear them manually, or you read the TAIV register to check which is the highest-priority IFG and this read will clear the IFG bit. If you don't clear the IFG bit this or that way (or reset the corresponding IE bit), the interrupt will be still pending and once you leave the ISR it will be immediately called again.

the UCxTXIFG bit is a good example: it is set once TXBUF is empty. If the ISR puts something into TXBUF, TXIFG is cleared. If not (because there's nothing to be sent), it remains set. either you clear it manually (then it stays clear) or you reset TXIE inside the ISR, so no more IRQ is requested. If you have something to send later, just set the TXIE bit again and the TX ISR will be fired and start sending again. For this to work, TXIFG must remain set until the software has handled the empty TXBUF. If TXIFG would be cleared the moment the ISR is entered, you could not stop and reactivate sending if there's nothing more to send. And the function adding something to send would have to check whether the TXBUF is really empty or if something unsent is still in it. It may not just set TXIFG again as this could cause a write to TXBUF while TXBUF is still filled.