MSP430F5342 DMA with SPI (UCB0/UCB1)

//!DONE	DMA macro definitions for module
#define	SR_DMATX			DMACTL0_L
#define	SR_DMARX			DMACTL0_H
#define	SR_DMATXCTL			DMA0CTL
#define	SR_DMATXTRG			DMACTL0_L
#define	SR_DMATXSA			DMA0SA
#define	SR_DMATXDA			DMA0DA
#define	SR_DMATXSZ			DMA0SZ
#define	SR_DMARXCTL			DMA1CTL
#define	SR_DMARXTRG			DMACTL0_H
#define	SR_DMARXSA			DMA1SA
#define	SR_DMARXDA			DMA1DA
#define	SR_DMARXSZ			DMA1SZ
#define	SR_DMA_RX_TRIG		DMA0TSEL__USCIB1RX
#define	SR_DMA_TX_TRIG		DMA0TSEL__USCIB1TX
#define	SR_DMA_BA			__MSP430_BASEADDRESS_USCI_B1__
#define	SR_BRATE			UCB1BRW

		// disable DMA
		SR_DMATXCTL = 0;
		// now set up the DMA
		SR_DMATXSA =	(void *)((uint8_t *)source);
		SR_DMATXDA =	(void*)&UCB1TXBUF;
		// set size
		SR_DMATXSZ =	size;
		//SR_DMARXSZ =	size;
		// set triggers
		//SR_DMATX =		SR_DMA_TX_TRIG;
		// set DMA to be interleaved with CPU activity
		DMACTL4 = 		ENNMI | DMARMWDIS;
		SR_DMARXCTL =	0;
		//SR_DMARX =		SR_DMA_RX_TRIG;
		DMACTL0 = 		((DMA0TSEL_0)<<8)|SR_DMA_TX_TRIG;
		// byte to byte source++ dest single transfer
		SR_DMATXCTL=	DMASBDB | DMASRCINCR_3 | DMADSTINCR_0 | DMADT_0 | DMAEN;
		// clear any interrupt flags
		SR_DMATXCTL &= ~DMAIFG;
		// initial trigger
		//UCB1TXBUF = *((uint8_t *)source);
		// toggle trigger to start DMA
		UCB1IFG &= ~UCTXIFG;
		UCB1IFG |= UCTXIFG;

		// disable TX DMA
		SR_DMATXCTL = 0;
		// now set up the DMA
		SR_DMATXSA =	(void *)&temp;
		SR_DMATXDA =	(void*)&UCB1TXBUF;
		// set size
		SR_DMATXSZ =	size;
		SR_DMARXSZ =	size;
		// set DMA to be interleaved with CPU activity
		DMACTL4 = 		DMARMWDIS;
		// disable RX DMA
		SR_DMARXCTL =	0;
		// note this can only be written as a word and both triggers
		// must be written simultaneously
		//DMACTL0 = (SR_DMA_RX_TRIG)<<8|SR_DMA_TX_TRIG;
		DMACTL0 =	DMA1TSEL__USCIB1RX | DMA0TSEL__USCIB1TX;
		//__data20_write_long
		SR_DMARXSA =	(void *)&UCB1RXBUF;
		SR_DMARXDA =	destination;
		// byte to byte source dest  single transfer
		SR_DMARXCTL =	DMASBDB | DMASRCINCR_0 | DMADSTINCR_3 | DMADT_0 | DMAEN;
		// byte to byte source++ dest  single transfer
		SR_DMATXCTL=	DMASBDB | DMASRCINCR_0 | DMADSTINCR_0 | DMADT_0 | DMAEN;
		// initial trigger
		UCB1IFG &= ~UCTXIFG;
		UCB1IFG |= UCTXIFG;