Other Parts Discussed in Thread: MSP430FR6972, MSP-TS430PM64F, MSP-FET
Part: MSP430FR6972. Project: BSL
We are using our standard serial (Host) interface that we’ve used for every product for bootstrap loading through the serial datacom port.
We have patched this interface into the MSP430FR6972 TXD and RXD BSL pins, P2.0 and P2.1 respectively using the MSP-TS430PM64F Target Socket board.
For the Target socket, we do not have anything plugged into the JTAG or BSL connectors. The jumper settings are as follows
- J1 -> 1-2 shorted
- JP1 -> closed
- JP2 -> closed
- JP3 -> 2-3 (UART)
- JP4 to JP8 -> 2-3 (4-wire JTAG mode)
- JP9 -> closed
- JP13 -> open
- JP14 -> closed
- JP15 -> closed
- JP16 -> 2-3 shorted (UART)
- JP17 and JP18 -> open
We use RTS/DTR from the host to provide the /RST and TEST signals required for the BSL entry sequence.
It seems that we satisfy the requirements as depicted in the Bootloader User’s Guide. However, when attempting to send a “Change Baud Rate command about 550ms after /RST goes back HIGH (when TEST is HIGH), but we never get any response from the MSP430.
Note we are able to communicate to and from the MSP430FR6962 when the application code is running, but for some reason either the BSL sequence is not working or the processor is not responding if it is indeed in bootloader mode.
Can you help? Is there something else that could interfere with the MSP430 from entering the bootloader program?
Here are some additional notes:
- We are using 9600, E, 8, 1 when communicating to the BSL and we assume it uses the same 5xx/6xx BSL protocol as the ‘5436A.
- TEST pulse (high level) meets duration based on tSBW,EN parameter .
- Modified the BSL entry sequence to mimic exact sequence as depicted in Figure 2 in the FR69xx bootloader user’s guide. (we removed the 1st 2 pulses as depicted in the original BSL plot attached)
- The supply voltage, VCC does not drop below its threshold during the sequence.
The only other question, is that I’m not exactly sure what it means by “JTAG has control over the MSP430’s resources” based on the statement below.
Therefore, can you ask if there is anything specific about the JTAG interface and/or state of the I/O pins (i.e. TDI, TCK, TDO, TEST, etc.?) that dictates to the ‘FR6972 that JTAG has control and BSL will not be allowed?