Other Parts Discussed in Thread: MSP430F2618
Hi all,
I've been working with SPI for a few years on an MSP430F2618 processor and now I'm getting it to work on an MSP432. I'm using 4-wire SPI and I'm at the point where the SPI communications seem to be happening correctly. I'm testing it by sending a single byte that's just being incremented by one every TX. However, after every transmit, the MOSI line stays at the level it was last at. When it's time for the next byte, it jumps back into writing out the byte within the CS Active Low time and the corresponding clock pulse. My logic analyzer can translate the data I'm trying to send correctly, which makes me think its working, but I feel like I've always seen the MOSI line return to a default logic level, but I've never really kept track of it. Here's a screenshot of what I'm seeing:
Does anyone know if the MOSI line needs to be returning to a level or is it simply a Don't Care condition if the CS isn't Active?
Thanks,
