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Clear TimerA From Hardware Pin

Other Parts Discussed in Thread: MSP430F5510, SN74LVC1G97, SN74AUP1G97

I am working on my first MSP430F5510 design (64 pin).

I understand how to generate PWM signals using TimerA in Up/Down counter mode. Is it possible to clear the timer using a signal on an MSP 430 pin instead of using an interrupt service routine? In other words, I would like to clear the timer when an MSP430 pin goes high and start counting again when the pin is low. Do I need to use a particular pin to reset the timer?

Thank you for your response.

Max

  • Hi Max!

    You may need to trigger on a pin interrupt and reconfigure the timer module in the port ISR. There is no "clear" or "restart" triggered by an external pin. Do you want to count or is it for PWM output? For counting you normally use the capture mode. And this can be triggered by an external pin.

    Dennis
  • To avoid any software, you could route one of the MSP's clocks to a pin, and use that signal as the external clock for the timer. You can then use a logic gate to block this signal.

    But why do you want to avoid the ISR? What problem would that solve?
  • Hello Dennis,

    Thank you for the quick reply. I am working on a project that is processing video signals from a camera. I have a horizontal sync signal (HS) that has a period of 64 us. HS is high for 5 us and low for 59 us. The MSP430 has a 24 MHz clock that I generate using the XT2 pins. This frequency is NOT synchronized to the HS signal.

    I want to configure a TimerA peripheral to generate two fixed frequency output signals. Each of the outputs is at 4 MHz. Each output is high for two clock periods and low for 4 clock periods. The two outputs should have a phase shift of 180 degrees and the high levels should not overlap. I understand how to configure the two clock outputs to generate the signals that I want. However, I cannot figure out how to "start" the sequence when HS transitions from high to low. Any interrupt latency would obviously defeat the timing that I need.

    Thanks in advance for any suggestions.
  • What is the largest allowed latency?

  • Hello Clemens,

    At most, one 24 MHz clock cycle.

    I am looking at the solution that you provided in your initial response. I think this will work, but it will unfortunately require some external logic circuitry, which I was trying to avoid as this is a super sensitive low cost application.

    Based on your recommendation, I could invert my HS signal and AND it with the system 24 MHz clock and feed this to the timer input clock. Then, I can generate an interrupt on the falling edge of the inverted HS signal and write code to clear the counter. The counter would start counting again when the inverted HS signal goes high.

    I'm assuming that I can feed the inverted HS signal to any pin to generate the interrupt on the falling edge of HS. I don't need to use a timer for this . . . correct?

    Thanks again for your help.
  • AND with one inverted input is a single logic gate (SN74LVC1G97 or SN74AUP1G97).

    Any P1.x or P2.x pin can raise an interrupt on a specific edge.
  • Thank you . . . your help is very much appreciated.

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