CC430 isr trap

celal ertug

Other Parts Discussed in Thread: CC430F5137

Hello ,

I'm using CC430F5137 wireless mcu. I work on a AMR project for watermeter.

CC430 works on wake on radio mode. 2-3 minutes after mcu start work, it enters isr trap. I defined every interrupt functions and nested interrupts is not used. But still mcu enter isr trap. Why mcu enters isr trap. What should i do to fix it ?

over 9 years ago

0 old_cow_yellow over 9 years ago

Guru 58965 points

Usually, if you enabled an interrupt without setting up an ISR for it, the CPU will be trapped when that interrupt actually happens.
Can you list of all the interrupts that you enabled?
Can you list all the ISR that you set up together with the starting address of each ISR?
Can you also list the contents of the Flash memory from 0xFFDA to 0xFFFF?

0 celal ertug over 9 years ago in reply to old_cow_yellow

Prodigy 60 points

flash memory contents

0x00FFDA __TI_int45
0x00FFDA AED6
0x00FFDC __TI_int46
0x00FFDC A136 FFFF
0x00FFE0 __TI_int48
0x00FFE0 B0BC
0x00FFE2 __TI_int49
0x00FFE2 B09E
0x00FFE4 __TI_int50
0x00FFE4 AED6
0x00FFE6 __TI_int51
0x00FFE6 B0F8
0x00FFE8 __TI_int52
0x00FFE8 AED6
0x00FFEA __TI_int53
0x00FFEA A0D2
0x00FFEC __TI_int54
0x00FFEC AED6
0x00FFEE __TI_int55
0x00FFEE B0DA
0x00FFF0 __TI_int56
0x00FFF0 AED6
0x00FFF2 __TI_int57
0x00FFF2 AED6
0x00FFF4 __TI_int58
0x00FFF4 B3C0
0x00FFF6 __TI_int59
0x00FFF6 AED6
0x00FFF8 __TI_int60
0x00FFF8 AED6
0x00FFFA __TI_int61
0x00FFFA B3C0
0x00FFFC __TI_int62
0x00FFFC B3C0
0x00FFFE _reset_vector

enabled interrupts :
timer0_a0
timer1_a0
rtc
cc_1101

this is my interrupt.c file.Every ISR adresses is written as comment ("__interrupt void timer0_a0_isr (void) //0xB0DA ")
all isr function prototype is defined in interrupt.h file and it's included in every file that called isr function

//////////////////////BEGINING OF THE FILE //////////////////////////////

void (*timer0_a0_isr_routine) (void) = NULL;
void (*timer0_a0_isr_routine2) (void) = NULL;

void interrupt_timer_register_fxn (void (*fxn)(void))
{
timer0_a0_isr_routine=fxn;
}

void interrupt_timer_register_fxn2 (void (*fxn)(void))
{
timer0_a0_isr_routine2=fxn;
}


#pragma vector=TIMER0_A0_VECTOR
__interrupt void timer0_a0_isr (void) //0xB0DA 
{
if(timer0_a0_isr_routine!=NULL)
timer0_a0_isr_routine();

//if(timer0_a0_isr_routine2!=NULL)
//timer0_a0_isr_routine2();

SYSENVMETHOD->post_swi();
__bic_SR_register_on_exit(LPM3_bits);
}

/******************************timer 1 interrupt*******************************/

void (*timer1_a0_isr_routine) (void) = NULL;

void interrupt_timer1_register_fxn (void (*fxn)(void))
{
timer1_a0_isr_routine=fxn;
}


#pragma vector=TIMER1_A0_VECTOR
__interrupt void timer1_a0_isr (void) //0xB0F8
{
if(timer1_a0_isr_routine!=NULL)
{
timer1_a0_isr_routine();
}
SYSENVMETHOD->post_swi();
__bic_SR_register_on_exit(LPM3_bits);
}


/******************************rtc interrupt*******************************/

void (*rtc_isr_readyread)(void)=NULL;
void (*rtc_isr_everymin)(void)=NULL;
void (*rtc_isr_alarm)(void)=NULL;


void interrupt_rtc_readyread_register_fxn (void (*fxn)(void))
{
rtc_isr_readyread=fxn;
}

void interrupt_rtc_everymin_register_fxn (void (*fxn)(void))
{
rtc_isr_everymin=fxn;
}

void interrupt_rtc_alarm_register_fxn (void (*fxn)(void))
{
rtc_isr_alarm=fxn;
}

#pragma vector=RTC_VECTOR
__interrupt void RTC_ISR(void) //0xA136
{
switch(__even_in_range(RTCIV,16))
{
case RTC_NONE: // No interrupts
break;
case RTC_RTCRDYIFG: // RTCRDYIFG //ready read
if(rtc_isr_readyread!=NULL)
{
rtc_isr_readyread();
SYSENVMETHOD->post_swi();
}
__bic_SR_register_on_exit(LPM3_bits);
break;
case RTC_RTCTEVIFG: // RTCEVIFG //event min
{
if(rtc_isr_everymin!=NULL)
{
rtc_isr_everymin();
SYSENVMETHOD->post_swi();
}
__no_operation(); // Interrupts every minute
__bic_SR_register_on_exit(LPM3_bits);

}
break;
case RTC_RTCAIFG: // RTCAIFG alarm service routine //alarm
{
if(rtc_isr_alarm!=NULL)
{
rtc_isr_alarm();
SYSENVMETHOD->post_swi();
}
__bic_SR_register_on_exit(LPM3_bits);

}
break;
case RTC_RT0PSIFG: // RT0PSIFG
break;
case RTC_RT1PSIFG: // RT1PSIFG
break;
case 12: break; // Reserved
case 14: break; // Reserved
case 16: break; // Reserved
default: break;
}

}


/****************************** port1 interrupt *******************************/

void (*port1_isr_routine)(void)=NULL;


void interrupt_port1_register_fxn (void (*fxn)(void))
{
port1_isr_routine=fxn;
}

#pragma vector = PORT1_VECTOR
__interrupt void port1_isr(void) { //0xB09E

if(port1_isr_routine!=NULL)
{
port1_isr_routine();
SYSENVMETHOD->post_swi();
}
__bic_SR_register_on_exit(LPM3_bits); // Exit active
}

/****************************** port2 interrupt *******************************/

void (*port2_isr_routine)(void)=NULL;


void interrupt_port2_register_fxn (void (*fxn)(void))
{
port2_isr_routine=fxn;
}

#pragma vector = PORT2_VECTOR
__interrupt void port2_isr(void) { //0xB0BC

if(port2_isr_routine!=NULL)
{
port2_isr_routine();
SYSENVMETHOD->post_swi();
}
__bic_SR_register_on_exit(LPM3_bits); // Exit active
}



/****************************** unused interrupt *******************************/
#pragma vector=TIMER0_A1_VECTOR
#pragma vector=TIMER1_A1_VECTOR
#pragma vector=WDT_VECTOR
//#pragma vector=RTC_VECTOR
//#pragma vector=PORT2_VECTOR
#pragma vector=AES_VECTOR
#pragma vector=DMA_VECTOR
#pragma vector=ADC12_VECTOR
#pragma vector=USCI_B0_VECTOR
#pragma vector=COMP_B_VECTOR
__interrupt void unused_isr (void) //0XAED6
{
/* Port 2 interrupt */
P2IE = 0;
/* AES interrupt */
AESACTL0 &= ~AESRDYIE;
/* DMA interrupt */
DMA0CTL &= ~DMAIE;
DMA1CTL &= ~DMAIE;
DMA2CTL &= ~DMAIE;
/* ADC */
ADC12IE = 0;
/* USCI_B */
UCB0IE = 0;
/* Comparator B */
CBINT = 0;
__no_operation();
__bic_SR_register_on_exit(LPM3_bits);
}

/****************************** cc1101 interrupt *******************************/

#pragma vector=CC1101_VECTOR // 0xA0D2 
__interrupt void CC1101_ISR(void)
{
switch(__even_in_range(RF1AIV,32)) // Prioritizing Radio Core Interrupt
{
case 0: break; // No RF core interrupt pending
case 2: break; // RFIFG0
case 4: //LNA_PD gdo1 interrupt
RF1AIE &= ~(BIT1 + BIT9);
Strobe(RF_SWOR);
break; // RFIFG1
case 6: break; // RFIFG2
case 8: break; // RFIFG3
case 10: break; // RFIFG4
case 12: break; // RFIFG5
case 14: break; // RFIFG6
case 16: break; // RFIFG7
case 18: break; // RFIFG8
case 20: // RFIFG9
if (radio_state==mode_rx)
{
stp_receiveslot(stp_cache);
}
if (radio_state==mode_tx)
{
RF1AIE &= ~BIT9; // Disable TX end-of-packet interrupt
stp_set_trover();
}
if(radio_state==mode_wor)
{
stp_wor_receiveslot();
}

case 22: break; // RFIFG10
case 24: break; // RFIFG11
case 26: break; // RFIFG12
case 28: break; // RFIFG13
case 30: //wor event0
stp_wor_event0();
break; // RFIFG14
case 32: break; // RFIFG15
}
__no_operation();
__bic_SR_register_on_exit(LPM3_bits);
}

//////////////////////END OF THE FILE//////////////////////////////

0 old_cow_yellow over 9 years ago in reply to celal ertug

Guru 58965 points

Sorry, I cannot figure out what went wrong.

Someone else please help.

0 Jace H over 9 years ago in reply to old_cow_yellow

TI__Guru 56685 points

Celal,

To clarify, when the error happens, is your CPU stuck somewhere or are you going into your defined unused ISR function?

0 celal ertug over 9 years ago in reply to Jace H

Prodigy 60 points

CPU is not stuck unused ISR function. I defined SYSNMI and UNMI ISR functions.Mostly CPU enters SYSNMI ISR function. I clear triggered interrupt flag when CPU enters SYSNMI isr but in this time i get osc fault and cpu get stuck somewhere else in my code. By the way i ' m using EM430F5137RF900 development board and i get this error all my EM430F5137RF900 boards.

0 Jace H over 9 years ago in reply to celal ertug

TI__Guru 56685 points

Celal,

With SNMI/UNMI''s you could be getting a few issues here. Oscillator Fault could be one so make sure you set up your clocks correctly and setup your Xtal properly. You could also be getting a PMM violation. I recommend only changing PMM settings with driverlib functions. that being said, more than likely you are getting a Flash Memory Access Violation or Vacant Memory Access violation. This means you could have an array out of bounds or a pointer pointing to an invalid part of memory. Please double check you array bounds, loop controls, and pointer usage for these possible errors.

0 celal ertug over 9 years ago in reply to Jace H

Prodigy 60 points

Thanks Jace
When mcu enter flash memory access or vacant memory access violation interrupt , heap parameters
(sys_base,sys_free,memsize) is changed. So i set write breakpoint on memsize variable. overflow of a global array causes
to change heap parameters thus mcu tries to allocate memory at invalid memory area. I fix it and problem solved.

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CC430 isr trap