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DMA with SPI relative clock speeds

A S
Intellectual 410 points

Out of curiosity, when using DMA over SPI, shouldn't the UCA/B CLK be going 4x as fast as MCLK in order to transfer the full byte in only 2 MCLK cycles? If so, how do you set the USCI clock to be 4x faster than the MCLK?

This question is for MSP430F5xxx series.

  • 0
    Guru 46710 points
    Why do you want that? Note that peripheral is requesting transfer, not DMA. I would like to free CPU bus for other stuff (than DMA), thus run MCLK at maximum rate, not try to make it slower.
  • 0 in reply to Ilmars
    Intellectual 410 points
    My question is referring to what it says in the www.ti.com/.../slau208o.pdf user guide that it takes the DMA 2 MCLK cycles to transfer 1 byte. I'm asking that if you use SPI as the trigger for DMA, will the SPI CLK be 4x as fast as MCLK?
  • 0 in reply to A S
    Guru 46710 points

    A S said:
    it takes the DMA 2 MCLK cycles to transfer 1 byte

    ... into destination which in this case is data register of SPI peripheral. After data is in register, SPI will shift it out using it's own clock (speed). Those are two separate operations - SPI data register write and SPI shift. You don't have to adjust DMA speed to SPI clock. Well, obviously you better run DMA and CPU (both running off MCLK) as fast as feasible for application.

    A S said:
    I'm asking that if you use SPI as the trigger for DMA, will the SPI CLK be 4x as fast as MCLK?

    No! SPI CLK can be 1x or 2x or 8x or 1000000x or whatever value possible by clock dividers, slower than MCLK - everything will be fine.

  • 0 in reply to Ilmars
    Intellectual 410 points

    Ilmars said:

    ... into destination which in this case is data register of SPI peripheral. After data is in register, SPI will shift it out using it's own clock (speed). Those are two separate operations - SPI data register write and SPI shift. You don't have to adjust DMA speed to SPI clock. Well, obviously you better run DMA and CPU (both running off MCLK) as fast as feasible for application.

    That part makes more sense now (2 MCLKs per byte shifted into SPI TX).

    My question for you then is this: When doing block DMA transfer to the SPI TX register, how is SPI able to transfer each consecutive byte from DMA back-to-back? Is DMA shifting data into the SPI TX register as fast as SPI is shifting it out?

  • 0 in reply to A S
    Guru 46710 points

    A S said:
    When doing block DMA transfer to the SPI TX register, how is SPI able to transfer each consecutive byte from DMA back-to-back?

    SPI does request new transfer from DMA only when needed (register empty). SPI regulates DMA transfer rate, not DMA. BTW it is kinda said before in this thread

  • 0 in reply to Ilmars
    Intellectual 410 points

    And does this SPI request from the DMA happen back-to-back for block DMA transfers? As in, there won't be any delay between consecutive bytes?

    I assume that the DMA transfer rate becomes the same as the SPI CLK rate? Then the "2 MCLK cycles per transfer" are irrelevant (i.e. concurrent with the SPI transfer)?

  • 0 in reply to A S
    Guru 46710 points

    A S said:
    I assume that the DMA transfer rate becomes the same as the SPI CLK rate?

    No. DMA transfer rate (transfers/sec) becomes the same as SPI word rate. If you send 8 bit words at 1MHz, then DMA transfers will be at 1/8 MHz frequency, each taking 2 MCLK cycles.

    A S said:
    Then the "2 MCLK cycles per transfer" are irrelevant (i.e. concurrent with the SPI transfer)?

    Indeed concurrent. That's why DMA was invented after all.

  • 0 in reply to Ilmars
    Intellectual 410 points

    Thank you for your patience in explaining this to me.

    As far as my other question regarding the back-to-back bytes being sent out of the SPI: does the DMA load the SPI TX register in some way that it can continuously shift out consecutive bytes back-to-back? Or is there a delay between emptying the SPI TX register and loading it again with the next byte from DMA? 

  • 0 in reply to A S
    Guru 99715 points
    I think the missing piece here is: There is a holding buffer in the SPI unit ahead of the Tx shift register. The DMA loads that, and it's moved (by the SPI unit) into the shift register when the shift register becomes empty.

    In order for the transmission to be continuous, the DMA only needs to load the holding buffer within the time it takes for the previous byte to shift out; since the DMA is signalled directly by the SPI unit (TXIFG) this isn't difficult.
  • 0 in reply to Bruce McKenney
    Guru 46710 points

    Bruce McKenney47378 said:
    In order for the transmission to be continuous, the DMA only needs to load the holding buffer within the time it takes for the previous byte to shift out; since the DMA is signalled directly by the SPI unit (TXIFG) this isn't difficult.

    Honestly - I don't know :) This is up-to SPI peripheral design. You shall read USCI chapter of your chip Users Manual carefully. Better just test it.

  • 0 in reply to Bruce McKenney
    Intellectual 410 points
    Thank you all for replying. These were the missing pieces!
  • 0 in reply to A S
    Guru 25210 points
    I thought it was explained in the other thread. As the others have said, the SPI module triggers the DMA engine.

    The SPI module has a TX buffer and a shift register. When the SPI module loads the shift register from the TX buffer, the TX buffer is then "empty" and sends a trigger signal to the DMA engine. While the SPI is shifting the data out of the shift register, the DMA engine concurrently fetches the next byte and writes it into the TX Buffer. When the SPI module is done shifting the bits from the previous byte, it looks and see that TX Buffer has the new byte, and the process repeats until the DMA engine has transferred all the bytes you programmed it to.

    If the SPI and DMA are running at the same rate, it takes 8 clocks to shift a byte out, and 6 clocks to transfer each byte into TX Buffer (setup + transfer + finish). This is because the DMA is moving single byte at a time. If you were doing block to block transfers it would be much more efficient.
  • 0 in reply to Brian Boorman
    Intellectual 310 points

    painfully simplistic question: I've a 6638 with an MCLK running at 20MHz. Is the fastest DMA driven SPI CLK 10MHz? (under the basis each DMA transfer takes 2 MCLKs?)

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