Other Parts Discussed in Thread: MSP430F5659
Hello fellow msp-ers
I'm creating code using an msp I've used before msp430f5659 and the EE changed the 4 MHz crystal to a 16 MHz
I changed the drive and the Dcorsel and expected that would be it, but unfortunately I've got an XT2OFFFG flag I can't figure out where it's coming from.
Can anyone find my flaw:
WDTCTL = WDTPW + WDTHOLD;
UCA0CTL1 = UCSWRST;
UCA0CTL0 = 0x00;
UCSCTL5 = 0x00; // ACLK, SMCLK source divider
istate_t istate = __get_interrupt_state();
__disable_interrupt(); // Disable global interrupts
UCSCTL6 = XT1OFF; // shut off xt1 clock
UCSCTL1 &= ~0x0070; // clear DCORE bits
UCSCTL1 |= DCORSEL_5;
UCSCTL6 &= ~XT2DRIVE_3; // clear the XT drive field
UCSCTL6 |= XT2DRIVE_1 ;// XT2DRIVE_0;
UCSCTL6 &= ~XT2OFF; // turn on xt2 clock source
P7SEL |= 0x0C; // use XT2 external crystal to create clock
// and turn off below
UCSCTL3 &= ~( FLLREFDIV0 | FLLREFDIV1 | FLLREFDIV2 );
// ref for fll is xt2clk / 2
UCSCTL3 = ((UCSCTL3 & ~(SELREF_7)) | (SELREF__XT2CLK ) | (FLLREFDIV_1)) ; //ref for fll is xt2clk
// AClk source = DCOclkdiv, SMClk source = XT2 , MCLK source = DCOclkdiv
UCSCTL4 = ((UCSCTL4 & ~(SELA_7)) | SELA__DCOCLKDIV| SELS__XT2CLK | SELM__DCOCLKDIV );
UCSCTL2 &= ~(0x03FF); // Reset FN bits
while (BAKCTL & LOCKBAK) // check if bit for backup subsystem is cleared
BAKCTL &= ~LOCKBAK;
SetVCore(2); // ok for both 16 MHz an 4 MHz
// Disable SVS
PMMCTL0_H = PMMPW_H; // PMM Password
SVSMHCTL &= ~(SVMHE+SVSHE); // Disable High side SVS
SVSMLCTL &= ~(SVMLE+SVSLE); // Disable Low side SVS
do
{ // clear all osc, DCO flags
UCSCTL7 &= ~ ( DCOFFG| XT1LFOFFG | XT1HFOFFG | XT2OFFG );
SFRIFG1 &= ~OFIFG;
} while(SFRIFG1 & OFIFG);
P1DIR = 0xFE;
// for trouble shooting below
P1SEL = 0x01; // set port 1 b1-7 as general i/o , bit 0 - ACLK
P1DIR = 0xff; // all port 1 bits outputs
// ** to begin, bring out smclk
// P3.4 SMCLK can be brought out with P3DIR.4 =1, P3SEL = 1
P3DIR = 0xff; // P3 all outputs
P3SEL |= 0x10; // bit 4 = SMCLK, rest general i/o
--------------------------------
I had wanted to bring out SMCLK and ACKL on their special function pins.
SMCLK = 15.9 MHz right now,
ACLK = nothing
I eventually want to make ACLK 8 MHz and use it as a source for uarts, etc.
But I can't do anything with this clock fault flag and I can't get anything to output on ACLK
Anyone have any ideas???
Any help would be much appreciated
Thanx!
Dubs
