Other Parts Discussed in Thread: MSP430F5438A
hi to all,
I am working with msp430f5438a microcontorller with your experimenter board MSP-EXP430F5438. In that i am working with ADC12_A(varaious resolution 8,10,12 bit) my problem is,
* For 8-bit adc Ideal SNR = 48dB around whereas we are getting around 42dB for a sinusoidal input. But, the SNR reaches to 48dB ie. below 20 HZ of input signal frequency. When increse in Frequency the SNR is deteriorating.
The operating condition of the ADC12_A
ADC12CLK = ADC12OSC (5MHZ)
SAMPLING TIME CLK CYCLES ADC12SHT0_0 = 4 ADC12CLK CYCLES
REFERENCE : Vr+ = VREF+ 2.5V ; Vr- = AVSS i.e ADC12SREF_1
I will attach my code below, and tell me the possible ranges to get Perfect SNR Ratio. If there is any parameter have to change let me know.
* I am using function generator as a analog input source with the external impedence (50 ohm - 1 M ohm), normally i am using 10 kohm;
My program :
#include "msp430f5438A.h"
#include <stdio.h>
void adc_function(void);
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
adc_function();
__bis_SR_register(LPM4_bits + GIE); // Enter LPM4, Enable interrupts
__no_operation(); // For debugger
}
void adc_function(void)
{
P6SEL |= 0x80; // Enable A/D channel A7
PBDIR = PBDIR | 0xFFFF;
REFCTL0 = REFMSTR + REFON + REFVSEL_2 + REFTCOFF;
ADC12CTL0 = ADC12ON+ADC12SHT0_0+ADC12MSC;
ADC12CTL1 = ADC12CSTARTADD_7 + ADC12SHP + ADC12SHS_0 + ADC12DIV_0 + ADC12SSEL_0 + ADC12CONSEQ_2;
ADC12CTL2 = ADC12RES_0;
ADC12MCTL7 = ADC12SREF_1 + ADC12INCH_7;
ADC12IE = ADC12IE7;
ADC12CTL0 |= ADC12ENC;
ADC12CTL0 |= ADC12SC;
}
// INTERRUPT VECTORS FOR MSP430 ////////////////////////////////////////
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADC12IV,34))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC overflow
case 4: break; // Vector 4: ADC timing overflow
case 6: break; // Vector 6: ADC12IFG0
case 8: break; // Vector 8: ADC12IFG1
case 10: break; // Vector 10: ADC12IFG2
case 12: break; // Vector 12: ADC12IFG3
case 14: break; // Vector 14: ADC12IFG4
case 16: break; // Vector 16: ADC12IFG5
case 18: break; // Vector 18: ADC12IFG6
case 20: // Vector 20: ADC12IFG7
PBOUT = ADC12MEM7;
case 22: break; // Vector 22: ADC12IFG8
case 24: break; // Vector 24: ADC12IFG9
case 26: break; // Vector 26: ADC12IFG10
case 28: break; // Vector 28: ADC12IFG11
case 30: break; // Vector 30: ADC12IFG12
case 32: break; // Vector 32: ADC12IFG13
case 34: break; // Vector 34: ADC12IFG14
default: break;
}
}
