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MSP430F2618 continuous ADC with DMA

Marten
Prodigy 80 points

Hi,

I am trying making a low power system that continuously samples data with ADC12 to a circular buffer and DMA in order to process them block based.

ADC is configured for repeated sequence of channels (16 channels, last has EOS set).

DMA is configured for repeated block transfer. It generates an interrupt when the 16 ADC samples are copied (source and destination address increment).

In order to have a buffer of more than 16 samples to process later, I am trying to change the DMA destination address inside the DMA interrupt to point to the next 16 samples.

Is this safe to do, because internally this DMA destination address is also updated. Is this new destination address being used for the next DMA transfer ?

Kind regards,

Marten

  • 0
    TI__Genius 15370 points

    Hi Marten, 

    You can only change the DMA destination address when transfers are disabled. This previous E2E post describes a process for ensuring that the no DMA transfers are trying to occur when changing this address: Change DMA Address While ADC Conversion.

    Let me know if you have any further questions!

    Best regards, 
    Caleb Overbay

  • 0 in reply to Caleb Overbay
    Prodigy 80 points

    Thanks for the answer  !

    I tried to update the destination address in the ISR and saw that the next block was still copied to the original buffer by DMA, but the transfer after that was using the updated destination address. But apparently it is not safe/reliable to do so.

    If I cannot change the address, I have to copy the data myself to the next part of the big buffer, but this is not a good solution.

    What is the best way to use such a continuous DMA and have a double buffer system ? Eg having 2 buffers of 128 samples, one being filled by ADC and DMA, the other one being processed ? Its a pity there is no half full DMA interrupt.

    Regards,

    Marten

  • 0 in reply to Marten
    TI__Genius 15370 points

    Hi Marten, 

    The DMA ISR fires when DMAxSZ reaches zero. This is after the contents have already been transferred to the location that was previously in the destination register. When you change the destination register in the interrupt, you are changing it for the next DMA transfer. This is risky though. When you change the destination register, the DMA is still enabled and a transfer could occur while you are changing the destination address. You need to ensure there is enough time between transfers to change the destination address without the possibility of another transfer starting.

    Maybe I'm not understanding what you are trying to do but I think the previous E2E post I linked to had an answer that detailed how to do what you are describing. 

    Best regards, 

    Caleb Overbay

  • 0 in reply to Caleb Overbay
    Prodigy 80 points
    Hi,

    The answer to that E2E post indeed looks interesting, although it is written a bit condensed.
    So the idea is to have 2 DMA channels, both using the ADC as source, starting DMA0 and then DMA1
    and relying on the DMA prio that DMA0 is started first.
    I would set both DMA sizes to 128 samples.
    The ADC is configured to repeated single channel.

    The time critical moment is when the ISR of DMA1 goes off, there DMA0 has to be started as soon
    as possible. When ADC sample (+conversion) frequency is set to 20K samples/s, it must be done within 50us.
    I don't know if this is feasible.

    I read the following E2E post where I read to use the 16 channels of the ADC:
    e2e.ti.com/.../56744

    So can the above idea with the 2 DMA channels also be used with the ADC configured to repeated
    sequence of channels.
    So DMA0 and DMA1 would be configured for single block transfer with the size of 16 samples.
    I think the only drawback is that the DMA interrupts will come every 16 samples instead of
    every 128 samples, but the interrupt latency time can now be 16 samples, so relaxing the critical
    time moment of above.

    Could you please comment on this?

    Kind regards,
    Marten

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