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MSP430F5438A PWM TB0 chan2

Jack Morrison
Prodigy 140 points
Other Parts Discussed in Thread: MSP430F5438, MSP430F5438A

I have an application generating multiple PWM outputs that works perfectly on a MSP430F5438 eval board. On a custom board with MSP430F5438A, some of the PWM channels aren't working right.

Initialization code includes:

// timer B0 = SMCLK(8.192MHz), 12 bit length, continuous mode,
// interrupt on TBIFG
TB0CTL = CNTL_1 + TBSSEL_2 + MC_2 + TBCLR + TBIE;
// TB0 counter 0 = interrupt on compare CCIFG
TB0CCTL0 = CCIE;

PWM duty cycle is set via TB0CCR1, TB0CCR2, etc.

At TBIV interrupt (2KHz), handler code includes:

	// all PWM outputs high
	TB0CCTL1 = OUTMOD_0 + 4;
	TB0CCTL2 = OUTMOD_0 + 4;
	// reset on count reached
	TB0CCTL1 = OUTMOD_5;
        TB0CCTL2 = OUTMOD_5;

So on the eval board, TB0 chan 1 and 2 work as expected (per scope trace). On the custom board, chan 1 is fine but chan 2 is always a very short duty cycle. If I move the "TB0CCTL2 = OUTMOD_5;" later in the ISR, the duty cycle is longer, so it appears that this immediately resets the output. If I disable that statement, the output is always high - so I think the hardware connections are ok. I can read back the correct limit count in TB0CCR2, and verified that TBCLGRP0 and CLLD are zero so there shouldn't be any group or delayed update of the latched limit TB0CL2 (which unfortunately can't be read). Nothing in the MSP430F5438A errata seems to apply.


Any suggestions?

  • 0
    Guru 316960 points
    Why are you changing TB0CCTLx in the interrupt handler? You do not need to do this to output a PWM signal.
  • 0 in reply to Clemens Ladisch
    Prodigy 140 points
    Thanks for responding. Normally you would be right, but I need 16 PWM outputs, and full hardware PWM is only supported on 12 (TA0_1-4, TA1_1-2, and TB0_1-6). So I have a messy scheme with interrupts (e.g. so TB0CCR0 isn't tied up).

    I tried a minimal test program that only does the PWM handling. On the '5438, all 16 channels are ok. On the '5438A, TB2, TB4, TB5, and TB6 have this behavior where TB0CCTLx = OUTMOD_5 immediately resets the output. TB1 and TB4 and all TA outputs are ok.

    After some experimenting, I found a workaround: Output Mode 1 works. So my ISR can clear the output (TB0CCTL2 = OUTMOD_0) then have it set at count reached (TB0CCTL2 = OUTMOD_1), and set the count (TB0CCR2) to the *low* PWM period.
  • 0 in reply to Jack Morrison
    Prodigy 140 points

    Followup, in case you're listening TI: I verified the same incorrect behavior with a commercial dev board using the MSP430F5438A. Sure looks like an anomaly with the chip.

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