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MSP432P401R: Program goes into a hard fault when array is variable size

Part Number: MSP432P401R

I am being plagued by a weird problem. At certain parts in my code (not at the beginning but somewhere around the middle and later) when I try initializing an array like so, or any variation there of: 

    int lengthi = 5;
    char d[lengthi];

My code goes into a Fault ISR loop. However when I do the following my code does not go into such a loop.

int lengthi = 5;
char d[5];

The registers when the program is in the faultISR are attached. My main thought is that this is a memory error, but increasing the and stack sizes doesn't do/help anything. Current sizes, set in Project->Properties->CCS Build->MSP432 Linker->Basic Options, are Stack 0x800 and Heap 0x1000

I can DM code if needed. I am using CCS 7.0

521177 14
R PC 0x0000000B 0x00004F4C
R SP 0x0000000B 0x2000FDC0
R LR 0x0000000B 0xFFFFFFE9
R xPSR 0x0000000B 0x01000003
R R0 0x0000000B 0x00000005
R R1 0x0000000B 0x00000005
R R2 0x0000000B 0x00000004
R R3 0x0000000B 0x00000138
R R4 0x0000000B 0x2000129C
R R5 0x0000000B 0x00000000
R R6 0x0000000B 0x00000008
R R7 0x0000000B 0x0A0D2C2C
R R8 0x0000000B 0x2000FE60
R R9 0x0000000B 0x00000000
R R10 0x0000000B 0x00000000
R R11 0x0000000B 0x00000000
R R12 0x0000000B 0x2000FF58
R R13 0x0000000B 0x2000FDC0
R R14 0x0000000B 0xFFFFFFE9
R MSP 0x0000000B 0x2000FDC0
R PSP 0x0000000B 0x00000000
R DSP 0x0000000B 0x00000000
R CTRL_FAULT_BASE_PRI 0x0000000B 0x00000000
R ADC14_ADC14CTL0 0x0000000B 0x00000000
R ADC14_ADC14CTL1 0x0000000B 0x00000030
R ADC14_ADC14LO0 0x0000000B 0x00000000
R ADC14_ADC14HI0 0x0000000B 0x00003FFF
R ADC14_ADC14LO1 0x0000000B 0x00000000
R ADC14_ADC14HI1 0x0000000B 0x00003FFF
R ADC14_ADC14MCTL0 0x0000000B 0x00000000
R ADC14_ADC14MCTL1 0x0000000B 0x00000000
R ADC14_ADC14MCTL2 0x0000000B 0x00000000
R ADC14_ADC14MCTL3 0x0000000B 0x00000000
R ADC14_ADC14MCTL4 0x0000000B 0x00000000
R ADC14_ADC14MCTL5 0x0000000B 0x00000000
R ADC14_ADC14MCTL6 0x0000000B 0x00000000
R ADC14_ADC14MCTL7 0x0000000B 0x00000000
R ADC14_ADC14MCTL8 0x0000000B 0x00000000
R ADC14_ADC14MCTL9 0x0000000B 0x00000000
R ADC14_ADC14MCTL10 0x0000000B 0x00000000
R ADC14_ADC14MCTL11 0x0000000B 0x00000000
R ADC14_ADC14MCTL12 0x0000000B 0x00000000
R ADC14_ADC14MCTL13 0x0000000B 0x00000000
R ADC14_ADC14MCTL14 0x0000000B 0x00000000
R ADC14_ADC14MCTL15 0x0000000B 0x00000000
R ADC14_ADC14MCTL16 0x0000000B 0x00000000
R ADC14_ADC14MCTL17 0x0000000B 0x00000000
R ADC14_ADC14MCTL18 0x0000000B 0x00000000
R ADC14_ADC14MCTL19 0x0000000B 0x00000000
R ADC14_ADC14MCTL20 0x0000000B 0x00000000
R ADC14_ADC14MCTL21 0x0000000B 0x00000000
R ADC14_ADC14MCTL22 0x0000000B 0x00000000
R ADC14_ADC14MCTL23 0x0000000B 0x00000000
R ADC14_ADC14MCTL24 0x0000000B 0x00000000
R ADC14_ADC14MCTL25 0x0000000B 0x00000000
R ADC14_ADC14MCTL26 0x0000000B 0x00000000
R ADC14_ADC14MCTL27 0x0000000B 0x00000000
R ADC14_ADC14MCTL28 0x0000000B 0x00000000
R ADC14_ADC14MCTL29 0x0000000B 0x00000000
R ADC14_ADC14MCTL30 0x0000000B 0x00000000
R ADC14_ADC14MCTL31 0x0000000B 0x00000000
R ADC14_ADC14MEM0 0x0000000B 0x00002049
R ADC14_ADC14MEM1 0x0000000B 0x00002049
R ADC14_ADC14MEM2 0x0000000B 0x000020E1
R ADC14_ADC14MEM3 0x0000000B 0x00000213
R ADC14_ADC14MEM4 0x0000000B 0x000000D0
R ADC14_ADC14MEM5 0x0000000B 0x00000A94
R ADC14_ADC14MEM6 0x0000000B 0x00001035
R ADC14_ADC14MEM7 0x0000000B 0x00002880
R ADC14_ADC14MEM8 0x0000000B 0x00000248
R ADC14_ADC14MEM9 0x0000000B 0x00000442
R ADC14_ADC14MEM10 0x0000000B 0x00000020
R ADC14_ADC14MEM11 0x0000000B 0x00000434
R ADC14_ADC14MEM12 0x0000000B 0x00001091
R ADC14_ADC14MEM13 0x0000000B 0x00002505
R ADC14_ADC14MEM14 0x0000000B 0x00002013
R ADC14_ADC14MEM15 0x0000000B 0x00000612
R ADC14_ADC14MEM16 0x0000000B 0x00003089
R ADC14_ADC14MEM17 0x0000000B 0x00000440
R ADC14_ADC14MEM18 0x0000000B 0x00000005
R ADC14_ADC14MEM19 0x0000000B 0x00000988
R ADC14_ADC14MEM20 0x0000000B 0x00000000
R ADC14_ADC14MEM21 0x0000000B 0x000030C9
R ADC14_ADC14MEM22 0x0000000B 0x00001828
R ADC14_ADC14MEM23 0x0000000B 0x00000A00
R ADC14_ADC14MEM24 0x0000000B 0x0000000F
R ADC14_ADC14MEM25 0x0000000B 0x00000628
R ADC14_ADC14MEM26 0x0000000B 0x00001113
R ADC14_ADC14MEM27 0x0000000B 0x00000001
R ADC14_ADC14MEM28 0x0000000B 0x00001102
R ADC14_ADC14MEM29 0x0000000B 0x00002000
R ADC14_ADC14MEM30 0x0000000B 0x00002E08
R ADC14_ADC14MEM31 0x0000000B 0x00002180
R ADC14_ADC14IER0 0x0000000B 0x00000000
R ADC14_ADC14IER1 0x0000000B 0x00000000
R ADC14_ADC14IFGR0 0x0000000B 0x00000000
R ADC14_ADC14IFGR1 0x0000000B 0x00000000
R ADC14_ADC14CLRIFGR0 0x0000000B 0x00000000
R ADC14_ADC14CLRIFGR1 0x0000000B 0x00000000
R ADC14_ADC14IV 0x0000000B 0x00000000
R AES256_AESACTL0 0x0000000F 0x0000
R AES256_AESACTL1 0x0000000F 0x0000
R AES256_AESASTAT 0x0000000F 0x0000
R AES256_AESAKEY 0x0000000F 0x0000
R AES256_AESADIN 0x0000000F 0x0000
R AES256_AESADOUT 0x0000000F 0x0000
R AES256_AESAXDIN 0x0000000F 0x0000
R AES256_AESAXIN 0x0000000F 0x0000
R CAPTIO0_CAPTIOCTL 0x0000000F 0x0000
R CAPTIO1_CAPTIOCTL 0x0000000F 0x0000
R COMP_E0_CECTL0 0x0000000F 0x0000
R COMP_E0_CECTL1 0x0000000F 0x0000
R COMP_E0_CECTL2 0x0000000F 0x0000
R COMP_E0_CECTL3 0x0000000F 0x0000
R COMP_E0_CEINT 0x0000000F 0x0000
R COMP_E0_CEIV 0x0000000F 0x0000
R COMP_E1_CECTL0 0x0000000F 0x0000
R COMP_E1_CECTL1 0x0000000F 0x0000
R COMP_E1_CECTL2 0x0000000F 0x0000
R COMP_E1_CECTL3 0x0000000F 0x0000
R COMP_E1_CEINT 0x0000000F 0x0000
R COMP_E1_CEIV 0x0000000F 0x0000
R COREDEBUG_DHCSR 0x0000000B 0x00030003
R COREDEBUG_DCRSR 0x0000000B 0x00000000
R COREDEBUG_DCRDR 0x0000000B 0x00000000
R COREDEBUG_DEMCR 0x0000000B 0x01000011
R CRC32_CRC32DI 0x0000000F 0x0000
R CRC32_CRC32DIRB 0x0000000F 0x0000
R CRC32_CRC32INIRES_LO 0x0000000F 0xFFFF
R CRC32_CRC32INIRES_HI 0x0000000F 0xFFFF
R CRC32_CRC32RESR_LO 0x0000000F 0xFFFF
R CRC32_CRC32RESR_HI 0x0000000F 0xFFFF
R CRC32_CRC16DI 0x0000000F 0x0000
R CRC32_CRC16DIRB 0x0000000F 0x0000
R CRC32_CRC16INIRES 0x0000000F 0xFFFF
R CRC32_CRC16RESR 0x0000000F 0xFFFF
R CS_CSKEY 0x0000000B 0x0000A596
R CS_CSCTL0 0x0000000B 0x0000165B
R CS_CSCTL1 0x0000000B 0x00000133
R CS_CSCTL2 0x0000000B 0x00070007
R CS_CSCTL3 0x0000000B 0x000000BB
R CS_CSCLKEN 0x0000000B 0x0000000F
R CS_CSSTAT 0x0000000B 0x1F0000A3
R CS_CSIE 0x0000000B 0x00000000
R CS_CSIFG 0x0000000B 0x00000001
R CS_CSCLRIFG 0x0000000B 0x00000000
R CS_CSSETIFG 0x0000000B 0x00000000
R CS_CSDCOERCAL0 0x0000000B 0x01810002
R CS_CSDCOERCAL1 0x0000000B 0x00000000
R PA_PAIN 0x0000000F 0x383C
R PA_PAOUT 0x0000000F 0xFF1B
R PA_PADIR 0x0000000F 0x0000
R PA_PAREN 0x0000000F 0x0000
R PA_PADS 0x0000000F 0x0000
R PA_PASEL0 0x0000000F 0x0000
R PA_PASEL1 0x0000000F 0x0000
R PA_PASELC 0x0000000F 0x0000
R PA_PAIES 0x0000000F 0xBDFB
R PA_PAIE 0x0000000F 0x0000
R PA_PAIFG 0x0000000F 0xA0D2
R P1_P1IV 0x0000000F 0x0000
R P1_P1IN 0x0000000D 0x3C
R P1_P1OUT 0x0000000D 0x1B
R P1_P1DIR 0x0000000D 0x00
R P1_P1REN 0x0000000D 0x00
R P1_P1DS 0x0000000D 0x00
R P1_P1SEL0 0x0000000D 0x00
R P1_P1SEL1 0x0000000D 0x00
R P1_P1SELC 0x0000000D 0x00
R P1_P1IES 0x0000000D 0xFB
R P1_P1IE 0x0000000D 0x00
R P1_P1IFG 0x0000000D 0xD2
R P2_P2IV 0x0000000F 0x0000
R P2_P2IN 0x0000000D 0x38
R P2_P2OUT 0x0000000D 0xFF
R P2_P2DIR 0x0000000D 0x00
R P2_P2REN 0x0000000D 0x00
R P2_P2DS 0x0000000D 0x00
R P2_P2SEL0 0x0000000D 0x00
R P2_P2SEL1 0x0000000D 0x00
R P2_P2SELC 0x0000000D 0x00
R P2_P2IES 0x0000000D 0xBD
R P2_P2IE 0x0000000D 0x00
R P2_P2IFG 0x0000000D 0xA0
R PB_PBIN 0x0000000F 0x00FE
R PB_PBOUT 0x0000000F 0xB7E5
R PB_PBDIR 0x0000000F 0x0020
R PB_PBREN 0x0000000F 0x0000
R PB_PBDS 0x0000000F 0x0000
R PB_PBSEL0 0x0000000F 0x000C
R PB_PBSEL1 0x0000000F 0x0000
R PB_PBSELC 0x0000000F 0x0000
R PB_PBIES 0x0000000F 0xBFFD
R PB_PBIE 0x0000000F 0x0000
R PB_PBIFG 0x0000000F 0x0033
R P3_P3IV 0x0000000F 0x0000
R P3_P3IN 0x0000000D 0xFE
R P3_P3OUT 0x0000000D 0xE5
R P3_P3DIR 0x0000000D 0x20
R P3_P3REN 0x0000000D 0x00
R P3_P3DS 0x0000000D 0x00
R P3_P3SEL0 0x0000000D 0x0C
R P3_P3SEL1 0x0000000D 0x00
R P3_P3SELC 0x0000000D 0x00
R P3_P3IES 0x0000000D 0xFD
R P3_P3IE 0x0000000D 0x00
R P3_P3IFG 0x0000000D 0x33
R P4_P4IV 0x0000000F 0x0000
R P4_P4IN 0x0000000D 0x00
R P4_P4OUT 0x0000000D 0xB7
R P4_P4DIR 0x0000000D 0x00
R P4_P4REN 0x0000000D 0x00
R P4_P4DS 0x0000000D 0x00
R P4_P4SEL0 0x0000000D 0x00
R P4_P4SEL1 0x0000000D 0x00
R P4_P4SELC 0x0000000D 0x00
R P4_P4IES 0x0000000D 0xBF
R P4_P4IE 0x0000000D 0x00
R P4_P4IFG 0x0000000D 0x00
R PC_PCIN 0x0000000F 0x0000
R PC_PCOUT 0x0000000F 0xBDD9
R PC_PCDIR 0x0000000F 0x0000
R PC_PCREN 0x0000000F 0x0000
R PC_PCDS 0x0000000F 0x0000
R PC_PCSEL0 0x0000000F 0x0000
R PC_PCSEL1 0x0000000F 0x0000
R PC_PCSELC 0x0000000F 0x0000
R PC_PCIES 0x0000000F 0x8DBF
R PC_PCIE 0x0000000F 0x0000
R PC_PCIFG 0x0000000F 0x0000
R P5_P5IV 0x0000000F 0x0000
R P5_P5IN 0x0000000D 0x00
R P5_P5OUT 0x0000000D 0xD9
R P5_P5DIR 0x0000000D 0x00
R P5_P5REN 0x0000000D 0x00
R P5_P5DS 0x0000000D 0x00
R P5_P5SEL0 0x0000000D 0x00
R P5_P5SEL1 0x0000000D 0x00
R P5_P5SELC 0x0000000D 0x00
R P5_P5IES 0x0000000D 0xBF
R P5_P5IE 0x0000000D 0x00
R P5_P5IFG 0x0000000D 0x00
R P6_P6IV 0x0000000F 0x0000
R P6_P6IN 0x0000000D 0x00
R P6_P6OUT 0x0000000D 0xBD
R P6_P6DIR 0x0000000D 0x00
R P6_P6REN 0x0000000D 0x00
R P6_P6DS 0x0000000D 0x00
R P6_P6SEL0 0x0000000D 0x00
R P6_P6SEL1 0x0000000D 0x00
R P6_P6SELC 0x0000000D 0x00
R P6_P6IES 0x0000000D 0x8D
R P6_P6IE 0x0000000D 0x00
R P6_P6IFG 0x0000000D 0x00
R PD_PDIN 0x0000000F 0x7C0F
R PD_PDOUT 0x0000000F 0x5FAF
R PD_PDDIR 0x0000000F 0x0000
R PD_PDREN 0x0000000F 0x0000
R PD_PDDS 0x0000000F 0x0000
R PD_PDSEL0 0x0000000F 0x0000
R PD_PDSEL1 0x0000000F 0x0000
R PD_PDSELC 0x0000000F 0x0000
R PD_PDIES 0x0000000F 0x0000
R PD_PDIE 0x0000000F 0x0000
R PD_PDIFG 0x0000000F 0x0000
R P7_P7IV 0x0000000F 0x0000
R P7_P7IN 0x0000000D 0x0F
R P7_P7OUT 0x0000000D 0xAF
R P7_P7DIR 0x0000000D 0x00
R P7_P7REN 0x0000000D 0x00
R P7_P7DS 0x0000000D 0x00
R P7_P7SEL0 0x0000000D 0x00
R P7_P7SEL1 0x0000000D 0x00
R P7_P7SELC 0x0000000D 0x00
R P7_P7IES 0x0000000D 0x00
R P7_P7IE 0x0000000D 0x00
R P7_P7IFG 0x0000000D 0x00
R P8_P8IV 0x0000000F 0x0000
R P8_P8IN 0x0000000D 0x7C
R P8_P8OUT 0x0000000D 0x5F
R P8_P8DIR 0x0000000D 0x00
R P8_P8REN 0x0000000D 0x00
R P8_P8DS 0x0000000D 0x00
R P8_P8SEL0 0x0000000D 0x00
R P8_P8SEL1 0x0000000D 0x00
R P8_P8SELC 0x0000000D 0x00
R P8_P8IES 0x0000000D 0x00
R P8_P8IE 0x0000000D 0x00
R P8_P8IFG 0x0000000D 0x00
R PE_PEIN 0x0000000F 0x01FC
R PE_PEOUT 0x0000000F 0x1E4E
R PE_PEDIR 0x0000000F 0x0000
R PE_PEREN 0x0000000F 0x0000
R PE_PEDS 0x0000000F 0x0000
R PE_PESEL0 0x0000000F 0x0000
R PE_PESEL1 0x0000000F 0x0000
R PE_PESELC 0x0000000F 0x0000
R PE_PEIES 0x0000000F 0x0000
R PE_PEIE 0x0000000F 0x0000
R PE_PEIFG 0x0000000F 0x0000
R P9_P9IV 0x0000000F 0x0000
R P9_P9IN 0x0000000D 0xFC
R P9_P9OUT 0x0000000D 0x4E
R P9_P9DIR 0x0000000D 0x00
R P9_P9REN 0x0000000D 0x00
R P9_P9DS 0x0000000D 0x00
R P9_P9SEL0 0x0000000D 0x00
R P9_P9SEL1 0x0000000D 0x00
R P9_P9SELC 0x0000000D 0x00
R P9_P9IES 0x0000000D 0x00
R P9_P9IE 0x0000000D 0x00
R P9_P9IFG 0x0000000D 0x00
R P10_P10IV 0x0000000F 0x0000
R P10_P10IN 0x0000000D 0x01
R P10_P10OUT 0x0000000D 0x1E
R P10_P10DIR 0x0000000D 0x00
R P10_P10REN 0x0000000D 0x00
R P10_P10DS 0x0000000D 0x00
R P10_P10SEL0 0x0000000D 0x00
R P10_P10SEL1 0x0000000D 0x00
R P10_P10SELC 0x0000000D 0x00
R P10_P10IES 0x0000000D 0x00
R P10_P10IE 0x0000000D 0x00
R P10_P10IFG 0x0000000D 0x00
R PJ_PJIN 0x0000000F 0x003C
R PJ_PJOUT 0x0000000F 0x0031
R PJ_PJDIR 0x0000000F 0x0000
R PJ_PJREN 0x0000000F 0x0000
R PJ_PJDS 0x0000000F 0x0000
R PJ_PJSEL0 0x0000000F 0x0030
R PJ_PJSEL1 0x0000000F 0x0000
R PJ_PJSELC 0x0000000F 0x0000
R DMA_DMA_DEVICE_CFG 0x0000000B 0x00000808
R DMA_DMA_SW_CHTRIG 0x0000000B 0x00000000
R DMA_DMA_CH0_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH1_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH2_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH3_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH4_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH5_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH6_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH7_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH8_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH9_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH10_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH11_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH12_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH13_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH14_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH15_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH16_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH17_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH18_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH19_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH20_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH21_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH22_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH23_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH24_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH25_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH26_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH27_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH28_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH29_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH30_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_CH31_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_INT1_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_INT2_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_INT3_SRCCFG 0x0000000B 0x00000000
R DMA_DMA_INT0_SRCFLG 0x0000000B 0x00000000
R DMA_DMA_INT0_CLRFLG 0x0000000B 0x00000000
R DMA_DMA_STAT 0x0000000B 0x10070000
R DMA_DMA_CFG 0x0000000B 0x00000000
R DMA_DMA_CTLBASE 0x0000000B 0x00000000
R DMA_DMA_ALTBASE 0x0000000B 0x00000080
R DMA_DMA_WAITSTAT 0x0000000B 0x00000000
R DMA_DMA_SWREQ 0x0000000B 0x00000000
R DMA_DMA_USEBURSTSET 0x0000000B 0x00000000
R DMA_DMA_USEBURSTCLR 0x0000000B 0x00000000
R DMA_DMA_REQMASKSET 0x0000000B 0x00000000
R DMA_DMA_REQMASKCLR 0x0000000B 0x00000000
R DMA_DMA_ENASET 0x0000000B 0x00000000
R DMA_DMA_ENACLR 0x0000000B 0x00000000
R DMA_DMA_ALTSET 0x0000000B 0x00000000
R DMA_DMA_ALTCLR 0x0000000B 0x00000000
R DMA_DMA_PRIOSET 0x0000000B 0x00000000
R DMA_DMA_PRIOCLR 0x0000000B 0x00000000
R DMA_DMA_ERRCLR 0x0000000B 0x00000000
R DWT_DWT_CTRL 0x0000000B 0x40000000
R DWT_DWT_CYCCNT 0x0000000B 0x00000000
R DWT_DWT_CPICNT 0x0000000B 0x00000000
R DWT_DWT_EXCCNT 0x0000000B 0x00000000
R DWT_DWT_SLEEPCNT 0x0000000B 0x00000000
R DWT_DWT_LSUCNT 0x0000000B 0x00000000
R DWT_DWT_FOLDCNT 0x0000000B 0x00000000
R DWT_DWT_PCSR 0x0000000B 0xFFFFFFFF
R DWT_DWT_COMP0 0x0000000B 0x00000000
R DWT_DWT_MASK0 0x0000000B 0x00000000
R DWT_DWT_FUNCTION0 0x0000000B 0x00000000
R DWT_DWT_COMP1 0x0000000B 0x00000000
R DWT_DWT_MASK1 0x0000000B 0x00000000
R DWT_DWT_FUNCTION1 0x0000000B 0x00000200
R DWT_DWT_COMP2 0x0000000B 0x00000000
R DWT_DWT_MASK2 0x0000000B 0x00000000
R DWT_DWT_FUNCTION2 0x0000000B 0x00000000
R DWT_DWT_COMP3 0x0000000B 0x00000000
R DWT_DWT_MASK3 0x0000000B 0x00000000
R DWT_DWT_FUNCTION3 0x0000000B 0x00000000
R EUSCI_A0_UCACTLW0 0x0000000F 0x0001
R EUSCI_A0_UCACTLW0_SPI 0x0000000F 0x0001
R EUSCI_A0_UCACTLW1 0x0000000F 0x0003
R EUSCI_A0_UCABRW 0x0000000F 0x0000
R EUSCI_A0_UCABRW_SPI 0x0000000F 0x0000
R EUSCI_A0_UCAMCTLW 0x0000000F 0x0000
R EUSCI_A0_UCASTATW 0x0000000F 0x0000
R EUSCI_A0_UCASTATW_SPI 0x0000000F 0x0000
R EUSCI_A0_UCARXBUF 0x0000000F 0x0000
R EUSCI_A0_UCARXBUF_SPI 0x0000000F 0x0000
R EUSCI_A0_UCATXBUF 0x0000000F 0x0000
R EUSCI_A0_UCATXBUF_SPI 0x0000000F 0x0000
R EUSCI_A0_UCAABCTL 0x0000000F 0x0000
R EUSCI_A0_UCAIRCTL 0x0000000F 0x0000
R EUSCI_A0_UCAIE 0x0000000F 0x0000
R EUSCI_A0_UCAIE_SPI 0x0000000F 0x0000
R EUSCI_A0_UCAIFG 0x0000000F 0x0002
R EUSCI_A0_UCAIFG_SPI 0x0000000F 0x0002
R EUSCI_A0_UCAIV 0x0000000F 0x0000
R EUSCI_A0_UCAIV_SPI 0x0000000F 0x0000
R EUSCI_A1_UCACTLW0 0x0000000F 0x0001
R EUSCI_A1_UCACTLW0_SPI 0x0000000F 0x0001
R EUSCI_A1_UCACTLW1 0x0000000F 0x0003
R EUSCI_A1_UCABRW 0x0000000F 0x0000
R EUSCI_A1_UCABRW_SPI 0x0000000F 0x0000
R EUSCI_A1_UCAMCTLW 0x0000000F 0x0000
R EUSCI_A1_UCASTATW 0x0000000F 0x0000
R EUSCI_A1_UCASTATW_SPI 0x0000000F 0x0000
R EUSCI_A1_UCARXBUF 0x0000000F 0x0000
R EUSCI_A1_UCARXBUF_SPI 0x0000000F 0x0000
R EUSCI_A1_UCATXBUF 0x0000000F 0x0000
R EUSCI_A1_UCATXBUF_SPI 0x0000000F 0x0000
R EUSCI_A1_UCAABCTL 0x0000000F 0x0000
R EUSCI_A1_UCAIRCTL 0x0000000F 0x0000
R EUSCI_A1_UCAIE 0x0000000F 0x0000
R EUSCI_A1_UCAIE_SPI 0x0000000F 0x0000
R EUSCI_A1_UCAIFG 0x0000000F 0x0002
R EUSCI_A1_UCAIFG_SPI 0x0000000F 0x0002
R EUSCI_A1_UCAIV 0x0000000F 0x0000
R EUSCI_A1_UCAIV_SPI 0x0000000F 0x0000
R EUSCI_A2_UCACTLW0 0x0000000F 0x0080
R EUSCI_A2_UCACTLW0_SPI 0x0000000F 0x0080
R EUSCI_A2_UCACTLW1 0x0000000F 0x0003
R EUSCI_A2_UCABRW 0x0000000F 0x0006
R EUSCI_A2_UCABRW_SPI 0x0000000F 0x0006
R EUSCI_A2_UCAMCTLW 0x0000000F 0x2081
R EUSCI_A2_UCASTATW 0x0000000F 0x0000
R EUSCI_A2_UCASTATW_SPI 0x0000000F 0x0000
R EUSCI_A2_UCARXBUF 0x0000000F 0x000A
R EUSCI_A2_UCARXBUF_SPI 0x0000000F 0x000A
R EUSCI_A2_UCATXBUF 0x0000000F 0x000A
R EUSCI_A2_UCATXBUF_SPI 0x0000000F 0x000A
R EUSCI_A2_UCAABCTL 0x0000000F 0x0000
R EUSCI_A2_UCAIRCTL 0x0000000F 0x0000
R EUSCI_A2_UCAIE 0x0000000F 0x0001
R EUSCI_A2_UCAIE_SPI 0x0000000F 0x0001
R EUSCI_A2_UCAIFG 0x0000000F 0x000E
R EUSCI_A2_UCAIFG_SPI 0x0000000F 0x000E
R EUSCI_A2_UCAIV 0x0000000F 0x0000
R EUSCI_A2_UCAIV_SPI 0x0000000F 0x0000
R EUSCI_A3_UCACTLW0 0x0000000F 0x0001
R EUSCI_A3_UCACTLW0_SPI 0x0000000F 0x0001
R EUSCI_A3_UCACTLW1 0x0000000F 0x0003
R EUSCI_A3_UCABRW 0x0000000F 0x0000
R EUSCI_A3_UCABRW_SPI 0x0000000F 0x0000
R EUSCI_A3_UCAMCTLW 0x0000000F 0x0000
R EUSCI_A3_UCASTATW 0x0000000F 0x0000
R EUSCI_A3_UCASTATW_SPI 0x0000000F 0x0000
R EUSCI_A3_UCARXBUF 0x0000000F 0x0000
R EUSCI_A3_UCARXBUF_SPI 0x0000000F 0x0000
R EUSCI_A3_UCATXBUF 0x0000000F 0x0000
R EUSCI_A3_UCATXBUF_SPI 0x0000000F 0x0000
R EUSCI_A3_UCAABCTL 0x0000000F 0x0000
R EUSCI_A3_UCAIRCTL 0x0000000F 0x0000
R EUSCI_A3_UCAIE 0x0000000F 0x0000
R EUSCI_A3_UCAIE_SPI 0x0000000F 0x0000
R EUSCI_A3_UCAIFG 0x0000000F 0x0002
R EUSCI_A3_UCAIFG_SPI 0x0000000F 0x0002
R EUSCI_A3_UCAIV 0x0000000F 0x0000
R EUSCI_A3_UCAIV_SPI 0x0000000F 0x0000
R EUSCI_B0_UCBCTLW0 0x0000000F 0x01C1
R EUSCI_B0_UCBCTLW0_SPI 0x0000000F 0x01C1
R EUSCI_B0_UCBCTLW1 0x0000000F 0x0000
R EUSCI_B0_UCBBRW 0x0000000F 0x0000
R EUSCI_B0_UCBBRW_SPI 0x0000000F 0x0000
R EUSCI_B0_UCBSTATW 0x0000000F 0x0000
R EUSCI_B0_UCBSTATW_SPI 0x0000000F 0x0000
R EUSCI_B0_UCBTBCNT 0x0000000F 0x0000
R EUSCI_B0_UCBRXBUF 0x0000000F 0x0000
R EUSCI_B0_UCBRXBUF_SPI 0x0000000F 0x0000
R EUSCI_B0_UCBTXBUF 0x0000000F 0x0000
R EUSCI_B0_UCBTXBUF_SPI 0x0000000F 0x0000
R EUSCI_B0_UCBI2COA0 0x0000000F 0x0000
R EUSCI_B0_UCBI2COA1 0x0000000F 0x0000
R EUSCI_B0_UCBI2COA2 0x0000000F 0x0000
R EUSCI_B0_UCBI2COA3 0x0000000F 0x0000
R EUSCI_B0_UCBADDRX 0x0000000F 0x0000
R EUSCI_B0_UCBADDMASK 0x0000000F 0x03FF
R EUSCI_B0_UCBI2CSA 0x0000000F 0x0000
R EUSCI_B0_UCBIE 0x0000000F 0x0000
R EUSCI_B0_UCBIE_SPI 0x0000000F 0x0000
R EUSCI_B0_UCBIFG 0x0000000F 0x0002
R EUSCI_B0_UCBIFG_SPI 0x0000000F 0x0002
R EUSCI_B0_UCBIV 0x0000000F 0x0000
R EUSCI_B0_UCBIV_SPI 0x0000000F 0x0000
R EUSCI_B1_UCBCTLW0 0x0000000F 0x01C1
R EUSCI_B1_UCBCTLW0_SPI 0x0000000F 0x01C1
R EUSCI_B1_UCBCTLW1 0x0000000F 0x0000
R EUSCI_B1_UCBBRW 0x0000000F 0x0000
R EUSCI_B1_UCBBRW_SPI 0x0000000F 0x0000
R EUSCI_B1_UCBSTATW 0x0000000F 0x0000
R EUSCI_B1_UCBSTATW_SPI 0x0000000F 0x0000
R EUSCI_B1_UCBTBCNT 0x0000000F 0x0000
R EUSCI_B1_UCBRXBUF 0x0000000F 0x0000
R EUSCI_B1_UCBRXBUF_SPI 0x0000000F 0x0000
R EUSCI_B1_UCBTXBUF 0x0000000F 0x0000
R EUSCI_B1_UCBTXBUF_SPI 0x0000000F 0x0000
R EUSCI_B1_UCBI2COA0 0x0000000F 0x0000
R EUSCI_B1_UCBI2COA1 0x0000000F 0x0000
R EUSCI_B1_UCBI2COA2 0x0000000F 0x0000
R EUSCI_B1_UCBI2COA3 0x0000000F 0x0000
R EUSCI_B1_UCBADDRX 0x0000000F 0x0000
R EUSCI_B1_UCBADDMASK 0x0000000F 0x03FF
R EUSCI_B1_UCBI2CSA 0x0000000F 0x0000
R EUSCI_B1_UCBIE 0x0000000F 0x0000
R EUSCI_B1_UCBIE_SPI 0x0000000F 0x0000
R EUSCI_B1_UCBIFG 0x0000000F 0x0002
R EUSCI_B1_UCBIFG_SPI 0x0000000F 0x0002
R EUSCI_B1_UCBIV 0x0000000F 0x0000
R EUSCI_B1_UCBIV_SPI 0x0000000F 0x0000
R EUSCI_B2_UCBCTLW0 0x0000000F 0x01C1
R EUSCI_B2_UCBCTLW0_SPI 0x0000000F 0x01C1
R EUSCI_B2_UCBCTLW1 0x0000000F 0x0000
R EUSCI_B2_UCBBRW 0x0000000F 0x0000
R EUSCI_B2_UCBBRW_SPI 0x0000000F 0x0000
R EUSCI_B2_UCBSTATW 0x0000000F 0x0000
R EUSCI_B2_UCBSTATW_SPI 0x0000000F 0x0000
R EUSCI_B2_UCBTBCNT 0x0000000F 0x0000
R EUSCI_B2_UCBRXBUF 0x0000000F 0x0000
R EUSCI_B2_UCBRXBUF_SPI 0x0000000F 0x0000
R EUSCI_B2_UCBTXBUF 0x0000000F 0x0000
R EUSCI_B2_UCBTXBUF_SPI 0x0000000F 0x0000
R EUSCI_B2_UCBI2COA0 0x0000000F 0x0000
R EUSCI_B2_UCBI2COA1 0x0000000F 0x0000
R EUSCI_B2_UCBI2COA2 0x0000000F 0x0000
R EUSCI_B2_UCBI2COA3 0x0000000F 0x0000
R EUSCI_B2_UCBADDRX 0x0000000F 0x0000
R EUSCI_B2_UCBADDMASK 0x0000000F 0x03FF
R EUSCI_B2_UCBI2CSA 0x0000000F 0x0000
R EUSCI_B2_UCBIE 0x0000000F 0x0000
R EUSCI_B2_UCBIE_SPI 0x0000000F 0x0000
R EUSCI_B2_UCBIFG 0x0000000F 0x0002
R EUSCI_B2_UCBIFG_SPI 0x0000000F 0x0002
R EUSCI_B2_UCBIV 0x0000000F 0x0000
R EUSCI_B2_UCBIV_SPI 0x0000000F 0x0000
R EUSCI_B3_UCBCTLW0 0x0000000F 0x01C1
R EUSCI_B3_UCBCTLW0_SPI 0x0000000F 0x01C1
R EUSCI_B3_UCBCTLW1 0x0000000F 0x0000
R EUSCI_B3_UCBBRW 0x0000000F 0x0000
R EUSCI_B3_UCBBRW_SPI 0x0000000F 0x0000
R EUSCI_B3_UCBSTATW 0x0000000F 0x0000
R EUSCI_B3_UCBSTATW_SPI 0x0000000F 0x0000
R EUSCI_B3_UCBTBCNT 0x0000000F 0x0000
R EUSCI_B3_UCBRXBUF 0x0000000F 0x0000
R EUSCI_B3_UCBRXBUF_SPI 0x0000000F 0x0000
R EUSCI_B3_UCBTXBUF 0x0000000F 0x0000
R EUSCI_B3_UCBTXBUF_SPI 0x0000000F 0x0000
R EUSCI_B3_UCBI2COA0 0x0000000F 0x0000
R EUSCI_B3_UCBI2COA1 0x0000000F 0x0000
R EUSCI_B3_UCBI2COA2 0x0000000F 0x0000
R EUSCI_B3_UCBI2COA3 0x0000000F 0x0000
R EUSCI_B3_UCBADDRX 0x0000000F 0x0000
R EUSCI_B3_UCBADDMASK 0x0000000F 0x03FF
R EUSCI_B3_UCBI2CSA 0x0000000F 0x0000
R EUSCI_B3_UCBIE 0x0000000F 0x0000
R EUSCI_B3_UCBIE_SPI 0x0000000F 0x0000
R EUSCI_B3_UCBIFG 0x0000000F 0x0002
R EUSCI_B3_UCBIFG_SPI 0x0000000F 0x0002
R EUSCI_B3_UCBIV 0x0000000F 0x0000
R EUSCI_B3_UCBIV_SPI 0x0000000F 0x0000
R FLCTL_FLCTL_POWER_STAT 0x0000000B 0x0000007C
R FLCTL_FLCTL_BANK0_RDCTL 0x0000000B 0x00003000
R FLCTL_FLCTL_BANK1_RDCTL 0x0000000B 0x00003000
R FLCTL_FLCTL_RDBRST_CTLSTAT 0x0000000B 0x00000000
R FLCTL_FLCTL_RDBRST_STARTADDR 0x0000000B 0x00000000
R FLCTL_FLCTL_RDBRST_LEN 0x0000000B 0x00000000
R FLCTL_FLCTL_RDBRST_FAILADDR 0x0000000B 0x00000000
R FLCTL_FLCTL_RDBRST_FAILCNT 0x0000000B 0x00000000
R FLCTL_FLCTL_PRG_CTLSTAT 0x0000000B 0x0000000C
R FLCTL_FLCTL_PRGBRST_CTLSTAT 0x0000000B 0x000000C0
R FLCTL_FLCTL_PRGBRST_STARTADDR 0x0000000B 0x00000000
R FLCTL_FLCTL_PRGBRST_DATA0_0 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA0_1 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA0_2 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA0_3 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA1_0 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA1_1 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA1_2 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA1_3 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA2_0 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA2_1 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA2_2 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA2_3 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA3_0 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA3_1 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA3_2 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_PRGBRST_DATA3_3 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_ERASE_CTLSTAT 0x0000000B 0x00000000
R FLCTL_FLCTL_ERASE_SECTADDR 0x0000000B 0x00000000
R FLCTL_FLCTL_BANK0_INFO_WEPROT 0x0000000B 0x00000003
R FLCTL_FLCTL_BANK0_MAIN_WEPROT 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_BANK1_INFO_WEPROT 0x0000000B 0x00000003
R FLCTL_FLCTL_BANK1_MAIN_WEPROT 0x0000000B 0xFFFFFFFF
R FLCTL_FLCTL_BMRK_CTLSTAT 0x0000000B 0x00000000
R FLCTL_FLCTL_BMRK_IFETCH 0x0000000B 0x00000000
R FLCTL_FLCTL_BMRK_DREAD 0x0000000B 0x00000000
R FLCTL_FLCTL_BMRK_CMP 0x0000000B 0x00010000
R FLCTL_FLCTL_IFG 0x0000000B 0x00000000
R FLCTL_FLCTL_IE 0x0000000B 0x00000000
R FLCTL_FLCTL_CLRIFG 0x0000000B 0x00000000
R FLCTL_FLCTL_SETIFG 0x0000000B 0x00000000
R FLCTL_FLCTL_READ_TIMCTL 0x0000000B 0x0064A037
R FLCTL_FLCTL_READMARGIN_TIMCTL 0x0000000B 0x0000005A
R FLCTL_FLCTL_PRGVER_TIMCTL 0x0000000B 0x0000A53F
R FLCTL_FLCTL_ERSVER_TIMCTL 0x0000000B 0x00000032
R FLCTL_FLCTL_LKGVER_TIMCTL 0x0000000B 0x0000005A
R FLCTL_FLCTL_PROGRAM_TIMCTL 0x0000000B 0xA0002D0F
R FLCTL_FLCTL_ERASE_TIMCTL 0x0000000B 0xA0AFC80F
R FLCTL_FLCTL_MASSERASE_TIMCTL 0x0000000B 0x00001040
R FLCTL_FLCTL_BURSTPRG_TIMCTL 0x0000000B 0x00000000
R FL_BOOTOVER_MAILBOX_MB_START 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_CMD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_SECEN 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_INIT_VECT 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_INIT_VECT 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_INIT_VECT 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_INIT_VECT 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_AES_SECKEYS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_UNENC_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_UNENC_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_UNENC_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_UNENC_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_ACK 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_BSL_ENABLE 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_BSL_START_ADDRESS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_BSL_PARAMETERS 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_BSL_ACK 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_ENCPAYLOADADD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_ENCPAYLOADLEN 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_JTAG_SWD_LOCK_DST_ADDR 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_ENC_UPDATE_ACK 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_ENABLE 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PWDEN 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PWD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PARAMS_ACK 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PASSWORD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PASSWORD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PASSWORD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_PASSWORD 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_FACTORY_RESET_ACK 0x0000000B 0xFFFFFFFF
R FL_BOOTOVER_MAILBOX_MB_END 0x0000000B 0xFFFFFFFF
R FPB_FP_CTRL 0x0000000B 0x00000261
R FPB_FP_REMAP 0x0000000B 0x20000000
R FPB_FP_COMP0 0x0000000B 0x80001881
R FPB_FP_COMP1 0x0000000B 0x800012B5
R FPB_FP_COMP2 0x0000000B 0x800048B9
R FPB_FP_COMP3 0x0000000B 0x40004ABD
R FPB_FP_COMP4 0x0000000B 0x00000000
R FPB_FP_COMP5 0x0000000B 0x00000000
R FPB_FP_COMP6 0x0000000B 0x00000000
R FPB_FP_COMP7 0x0000000B 0x00000000
R FPU_FPCCR 0x0000000B 0xC0000019
R FPU_FPCAR 0x0000000B 0x2000FDE0
R FPU_FPDSCR 0x0000000B 0x00000000
R FPU_MVFR0 0x0000000B 0x10110021
R FPU_MVFR1 0x0000000B 0x11000011
R ITM_ITM_STIM0 0x0000000B 0x00000001
R ITM_ITM_STIM1 0x0000000B 0x00000001
R ITM_ITM_STIM2 0x0000000B 0x00000001
R ITM_ITM_STIM3 0x0000000B 0x00000001
R ITM_ITM_STIM4 0x0000000B 0x00000001
R ITM_ITM_STIM5 0x0000000B 0x00000001
R ITM_ITM_STIM6 0x0000000B 0x00000001
R ITM_ITM_STIM7 0x0000000B 0x00000001
R ITM_ITM_STIM8 0x0000000B 0x00000001
R ITM_ITM_STIM9 0x0000000B 0x00000001
R ITM_ITM_STIM10 0x0000000B 0x00000001
R ITM_ITM_STIM11 0x0000000B 0x00000001
R ITM_ITM_STIM12 0x0000000B 0x00000001
R ITM_ITM_STIM13 0x0000000B 0x00000001
R ITM_ITM_STIM14 0x0000000B 0x00000001
R ITM_ITM_STIM15 0x0000000B 0x00000001
R ITM_ITM_STIM16 0x0000000B 0x00000001
R ITM_ITM_STIM17 0x0000000B 0x00000001
R ITM_ITM_STIM18 0x0000000B 0x00000001
R ITM_ITM_STIM19 0x0000000B 0x00000001
R ITM_ITM_STIM20 0x0000000B 0x00000001
R ITM_ITM_STIM21 0x0000000B 0x00000001
R ITM_ITM_STIM22 0x0000000B 0x00000001
R ITM_ITM_STIM23 0x0000000B 0x00000001
R ITM_ITM_STIM24 0x0000000B 0x00000001
R ITM_ITM_STIM25 0x0000000B 0x00000001
R ITM_ITM_STIM26 0x0000000B 0x00000001
R ITM_ITM_STIM27 0x0000000B 0x00000001
R ITM_ITM_STIM28 0x0000000B 0x00000001
R ITM_ITM_STIM29 0x0000000B 0x00000001
R ITM_ITM_STIM30 0x0000000B 0x00000001
R ITM_ITM_STIM31 0x0000000B 0x00000001
R ITM_ITM_TER 0x0000000B 0x00000000
R ITM_ITM_TPR 0x0000000B 0x00000000
R ITM_ITM_TCR 0x0000000B 0x00000000
R ITM_ITM_IWR 0x0000000B 0x00000000
R ITM_ITM_IMCR 0x0000000B 0x00000000
R ITM_ITM_LAR 0x0000000B 0x00000000
R ITM_ITM_LSR 0x0000000B 0x00000003
R MPU_MPU_TYPE 0x0000000B 0x00000800
R MPU_MPU_CTRL 0x0000000B 0x00000000
R MPU_MPU_RNR 0x0000000B 0x00000000
R MPU_MPU_RBAR 0x0000000B 0x00000000
R MPU_MPU_RASR 0x0000000B 0x00000000
R MPU_MPU_RBAR_A1 0x0000000B 0x00000000
R MPU_MPU_RASR_A1 0x0000000B 0x00000000
R MPU_MPU_RBAR_A2 0x0000000B 0x00000000
R MPU_MPU_RASR_A2 0x0000000B 0x00000000
R MPU_MPU_RBAR_A3 0x0000000B 0x00000000
R MPU_MPU_RASR_A3 0x0000000B 0x00000000
R NVIC_ISER0 0x0000000B 0x00040500
R NVIC_ISER1 0x0000000B 0x00000000
R NVIC_ICER0 0x0000000B 0x00040500
R NVIC_ICER1 0x0000000B 0x00000000
R NVIC_ISPR0 0x0000000B 0x00000010
R NVIC_ISPR1 0x0000000B 0x00000000
R NVIC_ICPR0 0x0000000B 0x00000010
R NVIC_ICPR1 0x0000000B 0x00000000
R NVIC_IABR0 0x0000000B 0x00000000
R NVIC_IABR1 0x0000000B 0x00000000
R NVIC_IPR0 0x0000000B 0x00000000
R NVIC_IPR1 0x0000000B 0x00000000
R NVIC_IPR2 0x0000000B 0x00000000
R NVIC_IPR3 0x0000000B 0x00000000
R NVIC_IPR4 0x0000000B 0x00000000
R NVIC_IPR5 0x0000000B 0x00000000
R NVIC_IPR6 0x0000000B 0x00000000
R NVIC_IPR7 0x0000000B 0x00000000
R NVIC_IPR8 0x0000000B 0x00000000
R NVIC_IPR9 0x0000000B 0x00000000
R NVIC_IPR10 0x0000000B 0x00000000
R NVIC_IPR11 0x0000000B 0x00000000
R NVIC_IPR12 0x0000000B 0x00000000
R NVIC_IPR13 0x0000000B 0x00000000
R NVIC_IPR14 0x0000000B 0x00000000
R NVIC_IPR15 0x0000000B 0x00000000
R NVIC_STIR 0x0000000B 0x00000000
R PCM_PCMCTL0 0x0000000B 0xA5960000
R PCM_PCMCTL1 0x0000000B 0xA5960000
R PCM_PCMIE 0x0000000B 0x00000000
R PCM_PCMIFG 0x0000000B 0x00000000
R PCM_PCMCLRIFG 0x0000000B 0x00000000
R PMAP_PMAPKEYID 0x0000000F 0x96A5
R PMAP_PMAPCTL 0x0000000F 0x0001
R PMAP_P1MAP01 0x0000000F 0x0000
R PMAP_P1MAP23 0x0000000F 0x0000
R PMAP_P1MAP45 0x0000000F 0x0000
R PMAP_P1MAP67 0x0000000F 0x0000
R PMAP_P2MAP01 0x0000000F 0x0807
R PMAP_P2MAP23 0x0000000F 0x0A09
R PMAP_P2MAP45 0x0000000F 0x1514
R PMAP_P2MAP67 0x0000000F 0x1716
R PMAP_P3MAP01 0x0000000F 0x0C0B
R PMAP_P3MAP23 0x0000000F 0x0E0D
R PMAP_P3MAP45 0x0000000F 0x100F
R PMAP_P3MAP67 0x0000000F 0x1211
R PMAP_P4MAP01 0x0000000F 0x0000
R PMAP_P4MAP23 0x0000000F 0x0000
R PMAP_P4MAP45 0x0000000F 0x0000
R PMAP_P4MAP67 0x0000000F 0x0000
R PMAP_P5MAP01 0x0000000F 0x0000
R PMAP_P5MAP23 0x0000000F 0x0000
R PMAP_P5MAP45 0x0000000F 0x0000
R PMAP_P5MAP67 0x0000000F 0x0000
R PMAP_P6MAP01 0x0000000F 0x0000
R PMAP_P6MAP23 0x0000000F 0x0000
R PMAP_P6MAP45 0x0000000F 0x0000
R PMAP_P6MAP67 0x0000000F 0x0000
R PMAP_P7MAP01 0x0000000F 0x1C1E
R PMAP_P7MAP23 0x0000000F 0x131D
R PMAP_P7MAP45 0x0000000F 0x1A1B
R PMAP_P7MAP67 0x0000000F 0x1819
R PSS_PSSKEY 0x0000000B 0x0000A596
R PSS_PSSCTL0 0x0000000B 0x00002000
R PSS_PSSIE 0x0000000B 0x00000000
R PSS_PSSIFG 0x0000000B 0x00000000
R PSS_PSSCLRIFG 0x0000000B 0x00000000
R REF_A_REFCTL0 0x0000000F 0x0008
R RSTCTL_RSTCTL_RESET_REQ 0x0000000B 0x00000000
R RSTCTL_RSTCTL_HARDRESET_STAT 0x0000000B 0x00000001
R RSTCTL_RSTCTL_HARDRESET_CLR 0x0000000B 0x00000000
R RSTCTL_RSTCTL_HARDRESET_SET 0x0000000B 0x00000000
R RSTCTL_RSTCTL_SOFTRESET_STAT 0x0000000B 0x00000000
R RSTCTL_RSTCTL_SOFTRESET_CLR 0x0000000B 0x00000000
R RSTCTL_RSTCTL_SOFTRESET_SET 0x0000000B 0x00000000
R RSTCTL_RSTCTL_PSSRESET_STAT 0x0000000B 0x0000000F
R RSTCTL_RSTCTL_PSSRESET_CLR 0x0000000B 0x00000000
R RSTCTL_RSTCTL_PCMRESET_STAT 0x0000000B 0x00000000
R RSTCTL_RSTCTL_PCMRESET_CLR 0x0000000B 0x00000000
R RSTCTL_RSTCTL_PINRESET_STAT 0x0000000B 0x00000000
R RSTCTL_RSTCTL_PINRESET_CLR 0x0000000B 0x00000000
R RSTCTL_RSTCTL_REBOOTRESET_STAT 0x0000000B 0x00000000
R RSTCTL_RSTCTL_REBOOTRESET_CLR 0x0000000B 0x00000000
R RSTCTL_RSTCTL_CSRESET_STAT 0x0000000B 0x00000000
R RSTCTL_RSTCTL_CSRESET_CLR 0x0000000B 0x00000000
R RTC_C_RTCCTL0 0x0000000F 0x9608
R RTC_C_RTCCTL13 0x0000000F 0x0070
R RTC_C_RTCOCAL 0x0000000F 0x0000
R RTC_C_RTCTCMP 0x0000000F 0x4000
R RTC_C_RTCPS0CTL 0x0000000F 0x0000
R RTC_C_RTCPS1CTL 0x0000000F 0x0000
R RTC_C_RTCPS 0x0000000F 0xFF81
R RTC_C_RTCIV 0x0000000F 0x0000
R RTC_C_RTCTIM0 0x0000000F 0x0617
R RTC_C_RTCTIM0_BCD 0x0000000F 0x0617
R RTC_C_RTCTIM1 0x0000000F 0x061F
R RTC_C_RTCTIM1_BCD 0x0000000F 0x061F
R RTC_C_RTCDATE 0x0000000F 0x0113
R RTC_C_RTCDATE_BCD 0x0000000F 0x0113
R RTC_C_RTCYEAR 0x0000000F 0x07FB
R RTC_C_RTCYEAR_BCD 0x0000000F 0x07FB
R RTC_C_RTCAMINHR 0x0000000F 0x0192
R RTC_C_RTCAMINHR_BCD 0x0000000F 0x0192
R RTC_C_RTCADOWDAY 0x0000000F 0x1C05
R RTC_C_RTCADOWDAY_BCD 0x0000000F 0x1C05
R RTC_C_RTCBIN2BCD 0x0000000F 0x0000
R RTC_C_RTCBCD2BIN 0x0000000F 0x0000
R SCB_CPUID 0x0000000B 0x410FC241
R SCB_ICSR 0x0000000B 0x00400803
R SCB_VTOR 0x0000000B 0x00000000
R SCB_AIRCR 0x0000000B 0xFA050000
R SCB_SCR 0x0000000B 0x00000000
R SCB_CCR 0x0000000B 0x00000200
R SCB_SHPR1 0x0000000B 0x00000000
R SCB_SHPR2 0x0000000B 0x00000000
R SCB_SHPR3 0x0000000B 0x00000000
R SCB_SHCSR 0x0000000B 0x00000000
R SCB_CFSR 0x0000000B 0x00008200
R SCB_HFSR 0x0000000B 0x40000000
R SCB_DFSR 0x0000000B 0x00000000
R SCB_MMFAR 0x0000000B 0x0A0D2C30
R SCB_BFAR 0x0000000B 0x0A0D2C30
R SCB_AFSR 0x0000000B 0x00000000
R SCB_PFR0 0x0000000B 0x00000030
R SCB_PFR1 0x0000000B 0x00000200
R SCB_DFR0 0x0000000B 0x00100000
R SCB_AFR0 0x0000000B 0x00000000
R SCB_MMFR0 0x0000000B 0x00100030
R SCB_MMFR1 0x0000000B 0x00000000
R SCB_MMFR2 0x0000000B 0x01000000
R SCB_MMFR3 0x0000000B 0x00000000
R SCB_ISAR0 0x0000000B 0x01101110
R SCB_ISAR1 0x0000000B 0x02112000
R SCB_ISAR2 0x0000000B 0x21232231
R SCB_ISAR3 0x0000000B 0x01111131
R SCB_ISAR4 0x0000000B 0x01310132
R SCB_CPACR 0x0000000B 0x00F00000
R SCnSCB_ICTR 0x0000000B 0x00000001
R SCnSCB_ACTLR 0x0000000B 0x00000000
R SYSCTL_SYS_REBOOT_CTL 0x0000000B 0x00000000
R SYSCTL_SYS_NMI_CTLSTAT 0x0000000B 0x00000007
R SYSCTL_SYS_WDTRESET_CTL 0x0000000B 0x00000003
R SYSCTL_SYS_PERIHALT_CTL 0x0000000B 0x00004000
R SYSCTL_SYS_SRAM_SIZE 0x0000000B 0x00010000
R SYSCTL_SYS_SRAM_BANKEN 0x0000000B 0x000100FF
R SYSCTL_SYS_SRAM_BANKRET 0x0000000B 0x00010001
R SYSCTL_SYS_FLASH_SIZE 0x0000000B 0x00040000
R SYSCTL_SYS_DIO_GLTFLT_CTL 0x0000000B 0x00000001
R SYSCTL_SYS_SECDATA_UNLOCK 0x0000000B 0x00000000
R SYSCTL_SYS_MASTER_UNLOCK 0x0000000B 0x00000000
R SYSCTL_SYS_BOOTOVER_REQ0 0x0000000B 0x00000000
R SYSCTL_SYS_BOOTOVER_REQ1 0x0000000B 0x00000000
R SYSCTL_SYS_BOOTOVER_ACK 0x0000000B 0x00000000
R SYSCTL_SYS_RESET_REQ 0x0000000B 0x00000000
R SYSCTL_SYS_RESET_STATOVER 0x0000000B 0x00000000
R SYSTICK_STCSR 0x0000000B 0x00000000
R SYSTICK_STRVR 0x0000000B 0x00000000
R SYSTICK_STCVR 0x0000000B 0x00000000
R SYSTICK_STCR 0x0000000B 0x00000000
R TIMER32_T32LOAD1 0x0000000B 0x00000000
R TIMER32_T32VALUE1 0x0000000B 0xFFFFFFFF
R TIMER32_T32CONTROL1 0x0000000B 0x00000020
R TIMER32_T32INTCLR1 0x0000000B 0x00000000
R TIMER32_T32RIS1 0x0000000B 0x00000000
R TIMER32_T32MIS1 0x0000000B 0x00000000
R TIMER32_T32BGLOAD1 0x0000000B 0x00000000
R TIMER32_T32LOAD2 0x0000000B 0x00000000
R TIMER32_T32VALUE2 0x0000000B 0xFFFFFFFF
R TIMER32_T32CONTROL2 0x0000000B 0x00000020
R TIMER32_T32INTCLR2 0x0000000B 0x00000000
R TIMER32_T32RIS2 0x0000000B 0x00000000
R TIMER32_T32MIS2 0x0000000B 0x00000000
R TIMER32_T32BGLOAD2 0x0000000B 0x00000000
R TIMER_A0_TACTL 0x0000000F 0x02C1
R TIMER_A0_TACCTL0 0x0000000F 0x0010
R TIMER_A0_TACCTL1 0x0000000F 0x0001
R TIMER_A0_TACCTL2 0x0000000F 0x0001
R TIMER_A0_TACCTL3 0x0000000F 0x0001
R TIMER_A0_TACCTL4 0x0000000F 0x0001
R TIMER_A0_TACCTL5 0x0000000F 0x0000
R TIMER_A0_TACCTL6 0x0000000F 0x0000
R TIMER_A0_TAR 0x0000000F 0x0000
R TIMER_A0_TACCR0 0x0000000F 0x004E
R TIMER_A0_TACCR1 0x0000000F 0x0000
R TIMER_A0_TACCR2 0x0000000F 0x0000
R TIMER_A0_TACCR3 0x0000000F 0x0000
R TIMER_A0_TACCR4 0x0000000F 0x0000
R TIMER_A0_TACCR5 0x0000000F 0x0000
R TIMER_A0_TACCR6 0x0000000F 0x0000
R TIMER_A0_TAEX0 0x0000000F 0x0007
R TIMER_A0_TAIV 0x0000000F 0x0000
R TIMER_A1_TACTL 0x0000000F 0x02C0
R TIMER_A1_TACCTL0 0x0000000F 0x0010
R TIMER_A1_TACCTL1 0x0000000F 0x0000
R TIMER_A1_TACCTL2 0x0000000F 0x0000
R TIMER_A1_TACCTL3 0x0000000F 0x0000
R TIMER_A1_TACCTL4 0x0000000F 0x0000
R TIMER_A1_TACCTL5 0x0000000F 0x0000
R TIMER_A1_TACCTL6 0x0000000F 0x0000
R TIMER_A1_TAR 0x0000000F 0x0000
R TIMER_A1_TACCR0 0x0000000F 0x3D09
R TIMER_A1_TACCR1 0x0000000F 0x0000
R TIMER_A1_TACCR2 0x0000000F 0x0000
R TIMER_A1_TACCR3 0x0000000F 0x0000
R TIMER_A1_TACCR4 0x0000000F 0x0000
R TIMER_A1_TACCR5 0x0000000F 0x0000
R TIMER_A1_TACCR6 0x0000000F 0x0000
R TIMER_A1_TAEX0 0x0000000F 0x0007
R TIMER_A1_TAIV 0x0000000F 0x0000
R TIMER_A2_TACTL 0x0000000F 0x0000
R TIMER_A2_TACCTL0 0x0000000F 0x0000
R TIMER_A2_TACCTL1 0x0000000F 0x0000
R TIMER_A2_TACCTL2 0x0000000F 0x0000
R TIMER_A2_TACCTL3 0x0000000F 0x0000
R TIMER_A2_TACCTL4 0x0000000F 0x0000
R TIMER_A2_TACCTL5 0x0000000F 0x0000
R TIMER_A2_TACCTL6 0x0000000F 0x0000
R TIMER_A2_TAR 0x0000000F 0x0000
R TIMER_A2_TACCR0 0x0000000F 0x0000
R TIMER_A2_TACCR1 0x0000000F 0x0000
R TIMER_A2_TACCR2 0x0000000F 0x0000
R TIMER_A2_TACCR3 0x0000000F 0x0000
R TIMER_A2_TACCR4 0x0000000F 0x0000
R TIMER_A2_TACCR5 0x0000000F 0x0000
R TIMER_A2_TACCR6 0x0000000F 0x0000
R TIMER_A2_TAEX0 0x0000000F 0x0000
R TIMER_A2_TAIV 0x0000000F 0x0000
R TIMER_A3_TACTL 0x0000000F 0x0000
R TIMER_A3_TACCTL0 0x0000000F 0x0000
R TIMER_A3_TACCTL1 0x0000000F 0x0000
R TIMER_A3_TACCTL2 0x0000000F 0x0000
R TIMER_A3_TACCTL3 0x0000000F 0x0000
R TIMER_A3_TACCTL4 0x0000000F 0x0000
R TIMER_A3_TACCTL5 0x0000000F 0x0000
R TIMER_A3_TACCTL6 0x0000000F 0x0000
R TIMER_A3_TAR 0x0000000F 0x0000
R TIMER_A3_TACCR0 0x0000000F 0x0000
R TIMER_A3_TACCR1 0x0000000F 0x0000
R TIMER_A3_TACCR2 0x0000000F 0x0000
R TIMER_A3_TACCR3 0x0000000F 0x0000
R TIMER_A3_TACCR4 0x0000000F 0x0000
R TIMER_A3_TACCR5 0x0000000F 0x0000
R TIMER_A3_TACCR6 0x0000000F 0x0000
R TIMER_A3_TAEX0 0x0000000F 0x0000
R TIMER_A3_TAIV 0x0000000F 0x0000
R TLV_TLV_CHECKSUM 0x0000000B 0x333063B6
R TLV_DEVICE_INFO_TAG 0x0000000B 0x0000000B
R TLV_DEVICE_INFO_LEN 0x0000000B 0x00000004
R TLV_DEVICE_ID 0x0000000B 0x0000A000
R TLV_HWREV 0x0000000B 0x00000042
R TLV_BCREV 0x0000000B 0x00410042
R TLV_ROM_DRVLIB_REV 0x0000000B 0x01010022
R TLV_DIE_REC_TAG 0x0000000B 0x0000000C
R TLV_DIE_REC_LEN 0x0000000B 0x00000008
R TLV_DIE_XPOS 0x0000000B 0x00001001
R TLV_DIE_YPOS 0x0000000B 0x00001007
R TLV_WAFER_ID 0x0000000B 0x00000580
R TLV_LOT_ID 0x0000000B 0x5536DE9A
R TLV_RESERVED0 0x0000000B 0xE2997C22
R TLV_RESERVED1 0x0000000B 0xFFFFFFFF
R TLV_RESERVED2 0x0000000B 0x00000000
R TLV_TEST_RESULTS 0x0000000B 0xFFFFFFFF
R TLV_CS_CAL_TAG 0x0000000B 0x00000003
R TLV_CS_CAL_LEN 0x0000000B 0x00000010
R TLV_DCOIR_FCAL_RSEL04 0x0000000B 0x00000161
R TLV_DCOIR_FCAL_RSEL5 0x0000000B 0xFFFFFFFF
R TLV_RESERVED3 0x0000000B 0x00000600
R TLV_RESERVED4 0x0000000B 0x00001600
R TLV_RESERVED5 0x0000000B 0x00000150
R TLV_RESERVED6 0x0000000B 0x00001600
R TLV_DCOIR_CONSTK_RSEL04 0x0000000B 0x3BA20147
R TLV_DCOIR_CONSTK_RSEL5 0x0000000B 0x3B9DF117
R TLV_DCOER_FCAL_RSEL04 0x0000000B 0x00000181
R TLV_DCOER_FCAL_RSEL5 0x0000000B 0xFFFFFFFF
R TLV_RESERVED7 0x0000000B 0x000005A0
R TLV_RESERVED8 0x0000000B 0x00001600
R TLV_RESERVED9 0x0000000B 0x00000140
R TLV_RESERVED10 0x0000000B 0x00001600
R TLV_DCOER_CONSTK_RSEL04 0x0000000B 0x3BA47ED0
R TLV_DCOER_CONSTK_RSEL5 0x0000000B 0x3B9FE868
R TLV_ADC14_CAL_TAG 0x0000000B 0x00000005
R TLV_ADC14_CAL_LEN 0x0000000B 0x00000018
R TLV_ADC_GAIN_FACTOR 0x0000000B 0xFFFFFFFF
R TLV_ADC_OFFSET 0x0000000B 0xFFFFFFFF
R TLV_RESERVED11 0x0000000B 0xFFFFFFFF
R TLV_RESERVED12 0x0000000B 0xFFFFFFFF
R TLV_RESERVED13 0x0000000B 0xFFFFFFFF
R TLV_RESERVED14 0x0000000B 0xFFFFFFFF
R TLV_RESERVED15 0x0000000B 0xFFFFFFFF
R TLV_RESERVED16 0x0000000B 0xFFFFFFFF
R TLV_RESERVED17 0x0000000B 0xFFFFFFFF
R TLV_RESERVED18 0x0000000B 0xFFFFFFFF
R TLV_RESERVED19 0x0000000B 0xFFFFFFFF
R TLV_RESERVED20 0x0000000B 0xFFFFFFFF
R TLV_RESERVED21 0x0000000B 0xFFFFFFFF
R TLV_RESERVED22 0x0000000B 0xFFFFFFFF
R TLV_RESERVED23 0x0000000B 0xFFFFFFFF
R TLV_RESERVED24 0x0000000B 0xFFFFFFFF
R TLV_RESERVED25 0x0000000B 0xFFFFFFFF
R TLV_RESERVED26 0x0000000B 0xFFFFFFFF
R TLV_ADC14_REF1P2V_TS30C 0x0000000B 0xFFFFFFFF
R TLV_ADC14_REF1P2V_TS85C 0x0000000B 0xFFFFFFFF
R TLV_ADC14_REF1P45V_TS30C 0x0000000B 0xFFFFFFFF
R TLV_ADC14_REF1P45V_TS85C 0x0000000B 0xFFFFFFFF
R TLV_ADC14_REF2P5V_TS30C 0x0000000B 0xFFFFFFFF
R TLV_ADC14_REF2P5V_TS85C 0x0000000B 0xFFFFFFFF
R TLV_REF_CAL_TAG 0x0000000B 0x00000008
R TLV_REF_CAL_LEN 0x0000000B 0x00000003
R TLV_REF_1P2V 0x0000000B 0xFFFFFFFF
R TLV_REF_1P45V 0x0000000B 0xFFFFFFFF
R TLV_REF_2P5V 0x0000000B 0xFFFFFFFF
R TLV_FLASH_INFO_TAG 0x0000000B 0x0000000D
R TLV_FLASH_INFO_LEN 0x0000000B 0x00000004
R TLV_FLASH_MAX_PROG_PULSES 0x0000000B 0x5A7B1D11
R TLV_FLASH_MAX_ERASE_PULSES 0x0000000B 0x1AF19BCF
R TLV_RANDOM_NUM_TAG 0x0000000B 0x874829DE
R TLV_RANDOM_NUM_LEN 0x0000000B 0xE1564735
R TLV_RANDOM_NUM_1 0x0000000B 0x0000000F
R TLV_RANDOM_NUM_2 0x0000000B 0x00000004
R TLV_RANDOM_NUM_3 0x0000000B 0xFFC2D0C0
R TLV_RANDOM_NUM_4 0x0000000B 0xFCFFFDA0
R TLV_BSL_CFG_TAG 0x0000000B 0xF0FF9770
R TLV_BSL_CFG_LEN 0x0000000B 0xFCFFFF72
R TLV_BSL_PERIPHIF_SEL 0x0000000B 0x0BD0E11D
R TLV_BSL_PORTIF_CFG_UART 0x0000000B 0xFFFFFFFF
R TLV_BSL_PORTIF_CFG_SPI 0x0000000B 0xFFFFFFFF
R TLV_BSL_PORTIF_CFG_I2C 0x0000000B 0xFFFFFFFF
R TLV_TLV_END 0x0000000B 0xFFFFFFFF
R WDT_A_WDTCTL 0x0000000F 0x6980

  • R SCB_CFSR 0x0000000B 0x00008200   <-- Bus Fault, Precise Error, BFAR valid
    R SCB_HFSR 0x0000000B 0x40000000   <-- Forced HardFault, because of unhandled MPU Fault, Bus Fault, or Usage Fault
    R SCB_DFSR 0x0000000B 0x00000000
    R SCB_MMFAR 0x0000000B 0x0A0D2C30  <-- Fault at Address
    R SCB_BFAR 0x0000000B 0x0A0D2C30   <-- Fault at Address

    What is this '0x0..0B' value (second column) supposed to mean ?

    Perhaps an alignment issue ?

    Can you post the relevant assembler code (the istructions preceeding and causing the fault) ?

  • f. m. said:
    What is this '0x0..0B' value (second column) supposed to mean ?

    The file was produced by an export from the Registers view in the CCS debugger. I can't find it documented what the second column is, but it appears the second column just encodes the width of the register. E.g. from looking at a sample of register exports on different devices:
    - One byte wide registers have a second column value of 0xD (as seen on a MSP432 device)
    - Two byte wide registers have a second column value of 0xF (as seen on a MSP432 device)
    - Four byte wide registers have a second column value of 0xB (as seen on a MSP432 or Cortex-A15 device)
    - Eight byte wide registers have a second column value of 0x19 (as seen on a Cortex-A15 device)

    Therefore, the value of the second column doesn't give any clue about the cause of the hard fault.

  • Hi Reid,

    judging from the register dump you provided, you have encountered a Bus Fault. The CFSR register is set to 0x8200 => precise bus error and the faulting address is saved in BFAR: 0x0A0D2C30. You can try to look in the disasembly of your executable for this address, maybe you'll find something useful (I am however afraid that you won't since usually this error means that there is nothing at the provided address or it is an invalid instruction).

    My guess is, that you are experiencing a linking issue and not including some memory management routine (probably malloc()) correctly. You could try to look in the disasembly how the array is initialized and if an external function is called, whether it is present in the binary.

    Also, are you sure that the TI compiler supports variable length arrays? And are you compiling with -c99 (although there should be an error, if you are not)?

    Cheers,

    Dan

  • The file was produced by an export from the Registers view in the CCS debugger...

    - Four byte wide registers have a second column value of 0xB (as seen on a MSP432 or Cortex-A15 device)
    - Eight byte wide registers have a second column value of 0x19 (as seen on a Cortex-A15 device)

    Therefore, the value of the second column doesn't give any clue about the cause of the hard fault.

    Thanks for the info, Chester.

    Dan Cermak said:
    Also, are you sure that the TI compiler supports variable length arrays? And are you compiling with -c99 (although there should be an error, if you are not)?

    The fact that the O.P. talks about runtime issues should be living proof that it builds without errors.

    Anyway, it is his (the O.P.'s) turn now ...

  • Reid Kersey said:
    My main thought is that this is a memory error, but increasing the and stack sizes doesn't do/help anything.

    Is your code bare-metal, or does it use some sort of RTOS?

    Looking at the assembler generated by the TI ARM compiler v16.9.0.LTS shows that when variable size arrays are used the compiler makes calls to the __vla_alloc() and __vla_dealloc() to allocate and deallocate space for the variable size arrays.

    The implementation for __vla_alloc() and __vla_dealloc() is in the lib\src\vla_alloc.cpp source file in the compiler installation. When I took a SYS/BIOS example with two threads, when a variable size array was used in two threads then the __vla_dealloc() function ended up aborting the program after detecting an assertion failure. I.e. the __vla_alloc() and __vla_dealloc() implementation doesn't appear to be thread safe.

  • Dan Cermak said:
    The CFSR register is set to 0x8200 => precise bus error and the faulting address is saved in BFAR: 0x0A0D2C30. You can try to look in the disasembly of your executable for this address, maybe you'll find something useful (I am however afraid that you won't since usually this error means that there is nothing at the provided address or it is an invalid instruction).

    In the MSP432P401R memory map the address 0x0A0D2C30 is Reserved.

    Therefore, the faulting address is probably caused by a bug / corruption of memory which leads to an invalid address being accessed.

  • Why would you need such a strange, rare C stuff?
    Your code will be much more foolproof if you do like this:

    #define ILENGTH 5
    int lengthi = ILENGTH;
    char d[ILENGTH];
  • I (implicitly) assume the given code are just examples of the method - us such, they would not make sense, compared to a direct, fixed-size definition.

    It makes sense if the size is e.g. given as function call parameter, and the array allocated inside a function. GCC supported this long before standard C, as a "language extension".

  • The code is Bare metal with driver lib. The code does fail at __vla_alloc(). It is also just an example. There are no errors generated when I build.

    I am leaning towards bug since this problem also happens with a fresh project.

    Specifically this code failes on this line of __vla_alloc():

       pool.allocations = (a_vla_allocation_ptr) malloc(
                                        pool.capacity * sizeof(a_vla_allocation));

    Causing This to happen:

     if (pool.allocations == NULL)
       {
          __abort_execution(ec_vla_allocation_failed);
       }   

    In malloc it returns null on this combination of lines:

        while (current && current->packet_size < newsize)
           current = current->size_ptr;
    
        if (!current)
        {
    	_unlock();
    	return NULL;
        }

    Export from CCS of variables at this point:

    current struct pack * 0x00000000 {packet_size=536936448,size_ptr=0x00004E71 {packet_size=2113404341,size_ptr=...} Register R7
        *(current) struct pack {packet_size=536936448,size_ptr=0x00004E71 {packet_size=2113404341,size_ptr=0x7BF7FFFF ...}} 0x00000000
            packet_size unsigned int 536936448 0x00000000
            size_ptr struct pack * 0x00004E71 {packet_size=2113404341,size_ptr=0x7BF7FFFF {packet_size=???} 0x00000004
                *(size_ptr) struct pack {packet_size=2113404341,size_ptr=0x7BF7FFFF {packet_size=???} 0x00004E71
                    packet_size unsigned int 2113404341 0x00004E71
                    size_ptr struct pack * 0x7BF7FFFF {packet_size=??? 0x00004E75


    newsize unsigned int 3004 Register R4
    oldsize unsigned int 2040 Register R5
    size unsigned int 3004 Register R4

  • I do not know how to post that. Could you please point me towards a example/tutorial?
  • Reid Kersey said:

    Causing This to happen:

     if (pool.allocations == NULL)
       {
          __abort_execution(ec_vla_allocation_failed);
       }   

    That suggests the heap is either:

    a) Too small for the required allocations.

    b) Becoming fragmented.

    c) Suffering from leaks.

    What is the size of the heap and what is the worst case allocation of variable size arrays?

    Does the program perform explicit dynamic memory allocation, as well as the implicit dynamic memory allocation performed by the variable size arrays?

  • I do not know how to post that. Could you please point me towards a example/tutorial?

    I think Chester is probably closer to the point, so I would concentrate on his suggestions.

    However, if you mean assembler code, that would depend on the toolchain. Most IDEs have either "mixed views" (i.e. C code and assembler, like the IAR WB), or separate "assembly views" in their debugger. And, of course, the core register contents are most useful in this case. The MSP432 as Cortex M device is a load/store architecture, thus the offending address usually turns up directly in a core register - usually R0 or R1.

    I'm no CCS user,so I can just point to the CCS tutorials at general.

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