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MSP432P401R: why 1024 alignment for dma control base

Eric Decker
Expert 1420 points

Part Number: MSP432P401R

I've noticed in the dma example programs for the msp432p401r using dma that an alignment constraint for the control block table of 1024 is used.

Everything I've read and even looking at how the h/w behaves tells me that this can actually be a 256 byte alignment.  Certainly, 1024 is aligned on a 256 boundary.

Is there any particular reason you folks have used the 1024 alignment?

Is there something I'm missing?

  • 0
    TI__Guru 63621 points
    Eric,
    The 1024 is unnecessary. The TRM states that the base address is an integer multiple of the total size of the channel control data structure (system memory requirements found on page 461 of the TRM, 9.2.4). I believe that the 1024 is simply a copy- paste error from the TRM based upon the example in figure 9-8 and the description of that example which is a 1024 alignment.

    In this specific iteration, the DMA only has 8 channels so the size is 256 as you point out and there is no need to align on 1024 boundaries. Interestingly in some of the older examples, before the DMA_ControlTable structure was available, the alignment was 256. (dev.ti.com/.../ )

    Best Regards,
    Chris

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