MSP430F5529: genration of pulse from [1 milli second to 15 sec] in steps of 1 milli second

hello ilmars,

                         i am using timer for pulse generation. my code is like below

WDTCTL = WDTPW | WDTHOLD;
set_clk();                             //16 Mhz sec
gpio_init();

//timer initialization

TA0CCTL0 = CCIE;
TA0CCR0 =3200;                        //500 usec
TA0CTL = TASSEL_2 | MC_1 | TACLR;
count=0;
n=(8000-1); //for 4 sec


#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void)

{
   	
	if(count<=n)P1OUT |= BIT0;
	else  if(count>n)
         {P1OUT &=~ BIT0;
          count=0;
          timer_disable();
         } 
	count++;		    				   			    
}

thanks

At a first glance I do not see anything that could cause cumulative error in your code. Could be so that for < 125ms pulses error is still there. Are you sure that SMCLK is running at expected frequency? - Route it to clock out pin and measure. What is your clock setup? 16MHz XT2 xtal, FLL with 32KHz crystal or just REFOCLK? Note that REFO have ~ +/- 3.5% tolerance (max temperature range).

void set_clk()
{

	UCSCTL3 |= SELREF_2;                   // select .... REFOCLK
	UCSCTL4 |= SELA_2;                     // REFOCLK.....use of Aclk    for smclk =SELS_2





	__bis_SR_register(SCG0);               // Disable the FLL control loop
	UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
	UCSCTL1 = DCORSEL_5;                   // Select DCO range 16MHz operation
	UCSCTL2 = FLLD_1 | 487;                // Set DCO Multiplier for 8MHz.....making of 16Mhz
	// (N + 1) * FLLRef = Fdco
	// (243 + 1) * 32768 = 8MHz    //(487+ 1) * 32768 = 16MHz
	// Set FLL Div = fDCOCLK/2
	__bic_SR_register(SCG0);               // Enable the FLL control loop

	// Worst-case settling time for the DCO when the DCO range bits have been
	// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
	// UG for optimization.
	// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
	__delay_cycles(500000);
	// __delay_cycles(76563);   //for 2.45Mhz

	// Loop until XT1, XT2 & DCO fault flag is cleared
	do
	{
		UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);  //XT2 oscillator fault flag|XT1 oscillator fault flag|DCO fault flag
		// Clear XT2,XT1,DCO fault flags
		SFRIFG1 &= ~OFIFG;                 // Clear fault flags
	} while (SFRIFG1 & OFIFG);             // Test oscillator fault flag

}

hello ilmars, my clock function is as above. i have checked SMCLK runs at 16 Mhz .

Well, you use REFO which at 25oC degrees have +/- 1.5% error. It is completely within spec if 4 sec pulses have range from 3940 to 4060 ms. Everything is ok in your design. If you need better precision - use higher precision reference oscillator (I mentioned already).

hello illmars,

                           how accurate a precision reference oscillator is going to be because  if i want to genrate 15000 ms pulse with 1 ms accuracy my clock should be has to be .003 % accurate atleast.

hello ilmars ,
thanks for your reply sir, i will check this and update you further.

EDITED : i checked this with 32768 hz crystal. i am now able to achieve 1 ms resolution.

A msp430 need to finish the current instruction before it jumps to a ISR, so you don't know if that is 1-3 cycles away.
So switch to hardware TA0CCR0 out, with clever divider options you should be able to get the large range of 1ms to 15'000ms

TA0CCR0 =3200-1;                        //500 usec << should use -1 as it restart at zero

On how many pins? plenty of timers and ccr's on a F5529 to get 3+ running at the same time on 8+ different pins.

Add the -1 to ccr0, should help with a uS drift.

ms delays should not happen unless you are using other large ISR that is hogging the system.

Use a 32K crystal, div TA0 by 8, you now get 0.244ms resolution and you get the whole range you need in a 16bit CCR.